SPRACR2 March   2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   Enabling Peripheral Expansion Applications Using the HIC
    1.     Trademarks
    2. 1 Introduction
    3. 2 HIC Configurations Overview
      1. 2.1 Access Modes
      2. 2.2 Data Width Selection
      3. 2.3 Base Address Selection
      4. 2.4 Read/write I/O Configuration
      5. 2.5 Device to Host Interrupts
        1. 2.5.1 Device Internal Events
        2. 2.5.2 Software Interrupts
    4. 3 Hardware Considerations
      1. 3.1 Common Signal Names
      2. 3.2 Address Pin Mapping
      3. 3.3 BASESEL Pin Mapping
    5. 4 Example Configuration for Pin Constrained Applications
      1. 4.1 Test Setup
      2. 4.2 Test Description
    6. 5 Example Configuration for Performance-Critical Applications
      1. 5.1 Test Setup
      2. 5.2 Test Description
    7. 6 Handling Device Reset and Low-Power Conditions
    8. 7 References
  2.   A Address Translation for Different Data Width Modes
    1.     A.1 Base Address and Offset Address Configuration

2.5.2 Software Interrupts

The HIC provides a software method to generate an interrupt to the Host. Any write into the HICD2HTOKEN register will trigger an interrupt on the HIC_INT pin. This method enables the extension of Host interrupt capability to Device peripherals that do not have direct interrupts mapped to the EVTRIG bus. For example, Figure 9 shows the Host-Device sequence to interrupt the Host CPU on a Device ADC End Of Conversion event.

Custom data exchange protocols can be implemented using the mailbox registers (D2H_BUFn and H2D_BUFn) and the token registers. For example, the Device can fill the D2H_BUFn registers with data to be exchanged and notify the Host by writing HICD2HTOKEN register with the number of words available in the D2H_BUFn registers.

spracr2-software-interrupt-usage-model.gifFigure 9. Software Interrupt Usage Model