SLVUAP9B May 2016 – October 2021 TPS54302
2.9 Powering Down
Figure 2-13 and Figure 2-14 show the start-up waveforms for the TPS54302EVM-716. In Figure 2-13, the output voltage ramps down as soon as the input voltage falls below the UVLO stop threshold as set by the R4 and R5 resistor divider network. In Figure 2-14, the output is inhibited by using a 3.3-V logic signal between EN and GND. The input voltage for these plots is 24 V and the load is 3.3 Ω.
Figure 2-13 TPS54302EVM-716 Shutdown Relative to VIN
Figure 2-14 TPS54302EVM-716 Shutdown Relative to EN