ZHCS952C June   2012  – January 2015 UCD8220-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CLK Input Time-Domain Digital Pulse Train
      2. 7.3.2 Current Sensing and Protection
      3. 7.3.3 Handshaking
      4. 7.3.4 Driver Output
      5. 7.3.5 Source and Sink Capabilities During Miller Plateau
      6. 7.3.6 Drive Current and Power Requirements
      7. 7.3.7 Clearing the Current-Limit Flag (CLF)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the ISET Resistor for Voltage Mode Control
        2. 8.2.2.2 Selecting the ISET Resistor for Voltage Mode Control with Voltage Feed Forward
        3. 8.2.2.3 Selecting the ISET Resistor for Peak Current Mode Control with Internal Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The UCD8220-Q1 device can be configured for either peak current mode or voltage mode control. The device can be used to implement a variety of applications such as push-pull, half-bridge, or full-bridge converter.

8.2 Typical Application

Using the UCD8220-Q1 device in an application, a high degree of digital control can be achieved because the device integrates the PWM, logic, error amplifier, current limit, and drivers. In addition, the on-chip regulator provides power to the microcontroller. An example application is using the device in half-bridge power topology.

UCD8220-Q1 d8220_hbcir_lus652.gif Figure 30. UCD8220-Q1 Typical Simplified Half-Bridge Converter Application Schematic

8.2.1 Design Requirements

When designing a half-bridge system, the key requirement is determining which functions should remain in the digital domain rather than the analog domain. The design shown in Figure 30 allows for a high degree of control over various blocks such as PWM, logic, error amplifier, current limit, and drivers. The UCD8220-Q1 closes the control loop for the power supply and provides the loop compensation. During operation, the UCD8220-Q1 monitors current and terminates the switching cycle safely if the value exceeds the current limit. By performing this task in the UCD8220-Q1, the device assists in real-time and full-time safety. The UCD8220-Q1 device provides notification of overcurrent events to the microcontroller. The notification of overcurrent events to the microcontroller allows the microcontroller to have a more complex response strategy. The firmware can, for example, direct the system to tolerate a finite number of current events, go to soft-stop, or shut down.

8.2.2 Detailed Design Procedure

Current limit is set through a simple resistor divider at the ISET pin. In the case of an overcurrent limit, the UCD8220-Q1 device sets the current flag (CF) pin high and the device is turned off by the host controller if the current limit exceeds a certain number of cycles. Depending upon the control method, the ISET resistor can be selected as previously mentioned.

8.2.2.1 Selecting the ISET Resistor for Voltage Mode Control

UCD8220-Q1 iset_vmc_slusb36.gif Figure 31. UCD8220-Q1 Configured in Voltage Mode Control With an Internal Timing Capacitor

When the ISET resistor is configured as shown in Figure 31 with the ISET resistor connected between the ISET pin and the 3V3 pin, the device is set up for voltage mode control. For purposes of voltage loop compensation the, voltage ramp is 1.4 V from the valley to the peak. Use Equation 5 to calculate the proper resistance for a desired clock frequency.

Equation 5. UCD8220-Q1 q1_r_iset_slusb36.gif

where

  • fclk = desired clock frequency in Hz
UCD8220-Q1 isetres_v_freq_lus652.gif Figure 32. ISET Resistance Versus Clock Frequency

Figure 32 shows the nominal value of resistance to use for a desired clock frequency. For example, a clock frequency of 1000 kHz will require 10 kΩ of the ISET resistor. The UCD8220-Q1 device has two outputs controlled by push-pull logic and therefore the output ripple frequency is equal to the clock frequency and each output switches at half the clock frequency.

8.2.2.2 Selecting the ISET Resistor for Voltage Mode Control with Voltage Feed Forward

UCD8220-Q1 iset_feedfwd_slusb36.gif Figure 33. UCD8220-Q1 Configured in Voltage Mode Control with Voltage Feed Forward

When the ISET resistor is configured as shown in Figure 33 with the ISET resistor connected between the ISET pin and the input voltage, VIN, the device is configured for voltage mode control with voltage feed forward. For the purposes of voltage loop compensation, the voltage ramp is 1.4 V × VIN / VIN_max from the valley to the peak. Use Equation 6 to calculate the proper resistance for a desired clock frequency and input voltage range.

Equation 6. UCD8220-Q1 q2_r_iset_slusb36.gif

where

  • fclk = Desired Clock Frequency in Hz

For a general discussion of the benefits of voltage mode control with voltage feed forward, see (5) in the 相关文档 section.

8.2.2.3 Selecting the ISET Resistor for Peak Current Mode Control with Internal Slope Compensation

UCD8220-Q1 iset_peak_slusb36.gif Figure 34. UCD8220-Q1 Configured in Peak Current Control with Internal Slope Compensation

When the ISET resistor is configured as shown in Figure 34 with the ISET resistor connected between the ISET pin and the AGND pin, the device is configured for peak current-mode control with internal slope compensation. The voltage at the ISET pin is 1.85 V so the internal slope compensation current, I_SC, being fed into the internal slope compensation capacitor is equal to 1.85 / (11 × R_ISET). Use Equation 7 to calculate the voltage slope at the PWM comparator input which is generated by this current.

Equation 7. UCD8220-Q1 q3_slope_slusb36.gif
UCD8220-Q1 slope_v_riset_lus65.gif Figure 35. Slope vs R_ISET Resistance

The amount of slope compensation required depends on the design of the power stage and the output specifications. A general rule is to add an up-slope equal to the down slope of the output inductor. Refer to (1) and (8) in the 相关文档 section for a more detailed discussion regarding slope compensation in peak current mode controlled power stages.

8.2.3 Application Curves

UCD8220-Q1 start_12v_3v3_slusb36.gif
CLK = CTRL = 3V3
Figure 36. Start-Up Behavior at VDD = 12 V
UCD8220-Q1 start_12v_gnd_slusb36.gif
CLK = AGND CTRL = 3V3
Figure 38. Start-Up Behavior at VDD = 12 V
UCD8220-Q1 shut_12v_3v3_slusb36.gif
CLK = CTRL = 3V3
Figure 37. Shut-Down Behavior at VDD = 12 V
UCD8220-Q1 shut_12v_gnd_slusb36.gif
CLK = AGND CTRL = 3V3
Figure 39. Shut-Down Behavior at VDD = 12 V