ZHCS952C June   2012  – January 2015 UCD8220-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CLK Input Time-Domain Digital Pulse Train
      2. 7.3.2 Current Sensing and Protection
      3. 7.3.3 Handshaking
      4. 7.3.4 Driver Output
      5. 7.3.5 Source and Sink Capabilities During Miller Plateau
      6. 7.3.6 Drive Current and Power Requirements
      7. 7.3.7 Clearing the Current-Limit Flag (CLF)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the ISET Resistor for Voltage Mode Control
        2. 8.2.2.2 Selecting the ISET Resistor for Voltage Mode Control with Voltage Feed Forward
        3. 8.2.2.3 Selecting the ISET Resistor for Peak Current Mode Control with Internal Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

MIN MAX UNIT
Supply voltage, VDD 16 V
Supply current, IDD Quiescent 20 mA
Switching, TA = 25°C, TJ = 125°C, VDD = 12 V 200
Output gate-drive voltage, VO OUTx –1 PVDD V
Output gate-drive sink current, IO(sink) OUTx 4 A
Output gate-drive source current, IO(source) OUTx –4
Analog input ISET, CS, CTRL, ILIM –0.3 3.6 V
Digital I/Os CLK, CLF –0.3 3.6
Continuous total power dissipation See Thermal Information
Operating junction temperature range, TJ –55 150 °C
Lead temperature (Soldering, 10 sec) 300 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 Corner pins (1, 8, 9, and 16) ±750
Other pins ±500
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage, PVDD 4.5 15.5 V

6.4 Thermal Information

THERMAL METRIC(1) PWP (HTSSOP) UNIT
16 PINS
RθJA Junction-to-ambient thermal resistance 40.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.5
RθJB Junction-to-board thermal resistance 24.2
ψJT Junction-to-top characterization parameter 1
ψJB Junction-to-board characterization parameter 24
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VDD = 12 V, 4.7-µF capacitor from VDD to AGND, 1 μF from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND, TA = TJ = –40°C to 125°C, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY SECTION
Supply current, OFF VDD = 4.2 V 300 500 µA
Supply current, ON Outputs not switching, CLK = low 1.6 3 mA
LOW VOLTAGE UNDERVOLTAGE LOCKOUT
VDD UVLO ON 4.25 4.5 4.75 V
VDD UVLO OFF 4.05 4.25 4.45 V
VDD UVLO hysteresis 150 250 350 mV
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point TA = 25°C, ILOAD = 0 3.267 3.3 3.333 V
3V3 set point over temperature 3.234 3.3 3.366 V
3V3 load regulation ILOAD = 1 mA to 10 mA, VDD = 5 V 1 6.6 mV
3V3 line regulation VDD = 4.75 V to 12 V, ILOAD = 10 mA 1 6.6 mV
Short circuit current VDD = 4.75 to 12 V 9 20 35 mA
3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1 V
3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9 V
CLOCK INPUT (CLK)
VIT+ HIGH, positive-going input threshold voltage 1.65 2.08 V
VIT– LOW negative-going input threshold voltage 1.16 1.5 V
(VIT+) – (VIT–) Input voltage hysteresis 0.6 0.8 V
Frequency OUTx = 1 MHz 2 MHz
SLOPE COMPENSATION (ISET)
ISET Voltage VISET , 3V3 = 3.3 V, ±2% 1.78 1.84 1.90 V
m VSLOPE (I-Mode) RISET = 6.19 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V 1.48 2.12 2.76 V/µs
RISET = 100 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V 0.099 0.142 0.185
RISET = 499 kΩ to AGND, CS = 0.25 V, CTRL = 2.5 V 0.019 0.028 0.037
m VSLOPE (V-Mode) RISET = 4.99 kΩ to 3V3, CTRL = 2.5 V 1.44 2.06 2.68 V/µs
RISET = 100 kΩ to 3V3, CTRL = 2.5 V 0.068 0.114 0.148
RISET = 402 kΩ to 3v3, CTRL = 2.5 V 0.016 0.027 0.035
ISET resistor range Current mode control; RISET connected to AGND 6.19 499 kΩ
ISET resistor range Voltage mode control; RISET connected to 3V3 4.99 402 kΩ
ISET current range Voltage mode control with Feed-Forward; RISET connected to VIN 3.7 300 μA
PWM
PWM offset at CTRL input 3V3 = 3.3 V ±2% 0.45 0.51 0.6 V
CTRL buffer gain(1) Gain from CTRL to PWM comparator input 0.5 V/V
CURRENT LIMIT (ILIM)
ILIM internal current limit threshold ILIM = OPEN 0.466 0.5 0.536 V
ILIM maximum current limit threshold ILIM = 3.3 V 0.975 1.025 1.075 V
ILIM current limit threshold ILIM = 0.75 V 0.700 0.725 0.750 V
ILIM minimum current limit threshold ILIM = 0.25 V 0.2 0.23 0.25 V
CLF output high level CS > ILIM , ILOAD = –7 mA 2.64 V
CLF output low level CS ≤ ILIM, ILOAD = 7 mA 0.66 V
CURRENT SENSE COMPARATOR
Bias voltage Includes CS comp offset 5 25 50 mV
Input bias current –1 μA
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance CLK = low, resistance from CS to AGND 10 35 75 Ω
OUTPUT DRIVERS
Source current(1) VDD = 12 V, CLK = high, OUTx = 5 V 4 A
Sink current(1) VDD = 12 V, CLK = low, OUTx = 5 V 4 A
Source current(1) VDD = 4.75 V, CLK = high, OUTx = 0 2 A
Sink current(1) VDD = 4.75 V, CLK = low, OUTx = 4.75 V 3 A
Output with VDD < UVLO VDD = 1.0 V, ISINK = 10 mA 0.8 1.2 V
(1) Specified by design. Not 100% tested in production.

6.6 Timing Requirements

VDD = 12 V, 4.7-µF capacitor from VDD to AGND, 1 μF from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND, TA = TJ = –40°C to 125°C, (unless otherwise noted).
MIN NOM MAX UNIT
CLOCK INPUT (CLK)
Minimum allowable off time(1) 20 ns
CURRENT LIMIT (ILIM)
Propagation delay from CLK to CLF CLK rising to CLF falling after a current limit event 15 25 ns
CURRENT SENSE COMPARATOR
Propagation delay from CS to OUTx ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV 25 40 ns
Propagation delay from CS to CLF ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV 25 50
OUTPUT DRIVERS
tR Rise time CLOAD = 2.2 nF, VDD = 12 V, See Figure 1 10 20 ns
tF Fall time CLOAD = 2.2 nF, VDD = 12 V, See Figure 1 10 15
tD1 Propagation delay from CLK to OUTx, CLK rising CLOAD = open, VDD = 12 V, See Figure 1 25 35 ns
tD2 Propagation delay from CLK to OUTx, CLK falling CLOAD = open, VDD = 12 V, See Figure 1 25 35
UCD8220-Q1 time_diag_slusb36.gif Figure 1. Timing Diagram

6.7 Typical Characteristics

UCD8220-Q1 uvlo_v_temp_slusb36.gif Figure 2. UCD8220-Q1 UVLO Threshold vs Temperature
UCD8220-Q1 v33scc_v_temp_slusb36.gif Figure 4. 3V3 Short-circuit Current vs Temperature
UCD8220-Q1 v33ref_v_temp_slusb36.gif Figure 3. 3V3 Reference Voltage vs Temperature
UCD8220-Q1 idd_5v_freq_slusb36.gif Figure 5. Supply Current vs Frequency (VDD = 5 V)
UCD8220-Q1 idd_8v_freq_slusb36.gif Figure 6. Supply Current vs Frequency (VDD = 8 V)
UCD8220-Q1 idd_12v_freq_slusb36.gif Figure 8. Supply Current vs Frequency (VDD = 12 V)
UCD8220-Q1 vi_v_temp_slusb36.gif
Figure 10. CLK Input Threshold vs Temperature
UCD8220-Q1 ir_v_vdd_slusb36.gif
Figure 12. Output Rise Time vs Supply Voltage
UCD8220-Q1 tpd_rise_vdd_slusb36.gif Figure 14. CLK to OUTx Propagation Delay Rising vs Supply Voltage
UCD8220-Q1 vcs_v_temp_slusb36.gif Figure 16. Default Current Limit Threshold vs Temperature
UCD8220-Q1 tpd_2cs_temp_slusb36.gif Figure 18. CS to CLF Propagation Delay vs Temperature
UCD8220-Q1 start_12v_3v3_slusb36.gif
CLK = CTRL = 3V3
Figure 20. Start-Up Behavior at VDD = 12 V
UCD8220-Q1 start_12v_gnd_slusb36.gif
CLK = AGND CTRL = 3V3
Figure 22. Start-Up Behavior at VDD = 12 V
UCD8220-Q1 vo_v_time_slusb36.gif
VDD = 12 V CLOAD = 10 nF
Figure 24. Output Rise and Fall Time
UCD8220-Q1 pwmoff_v_temp_slusb36.gif
Figure 26. PWM Offset at CTRL Input vs Temperature
UCD8220-Q1 idd_10v_freq_slusb36.gif Figure 7. Supply Current vs Frequency (VDD = 10 V)
UCD8220-Q1 idd_15v_freq_slusb36.gif Figure 9. Supply Current vs Frequency (VDD = 15 V)
UCD8220-Q1 irif_v_temp_slusb36.gif
CLOAD = 2.2 nF VDD = 12 V
Figure 11. Output Rise Time and Fall Time vs Temperature
UCD8220-Q1 if_v_vdd_slusb36.gif
Figure 13. Output Fall Time vs Supply Voltage
UCD8220-Q1 tpd_fall_vdd_slusb36.gif Figure 15. CLK to OUTx Propagation Delay Falling vs Supply Current
UCD8220-Q1 tpd_1cs_temp_slusb36.gif Figure 17. CS to OUTx Propagation Delay vs Temperature
UCD8220-Q1 tpd_3cs_temp_slusb36.gif Figure 19. CLK to OUT Propagation Delay vs Temperature
UCD8220-Q1 shut_12v_3v3_slusb36.gif
CLK = CTRL = 3V3
Figure 21. Shut-Down Behavior at VDD = 12 V
UCD8220-Q1 shut_12v_gnd_slusb36.gif
CLK = AGND CTRL = 3V3
Figure 23. Shut-Down Behavior at VDD = 12 V
UCD8220-Q1 intslp_v_temp_slusb36.gif
Current mode slope RISET = 100 kΩ
Figure 25. Internal Slope Compensation in CMC vs Temperature