ZHCS952C June   2012  – January 2015 UCD8220-Q1

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CLK Input Time-Domain Digital Pulse Train
      2. 7.3.2 Current Sensing and Protection
      3. 7.3.3 Handshaking
      4. 7.3.4 Driver Output
      5. 7.3.5 Source and Sink Capabilities During Miller Plateau
      6. 7.3.6 Drive Current and Power Requirements
      7. 7.3.7 Clearing the Current-Limit Flag (CLF)
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selecting the ISET Resistor for Voltage Mode Control
        2. 8.2.2.2 Selecting the ISET Resistor for Voltage Mode Control with Voltage Feed Forward
        3. 8.2.2.3 Selecting the ISET Resistor for Peak Current Mode Control with Internal Slope Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout

Layout Guidelines

In a MOSFET driver operating at high frequency, minimizing stray inductance to minimize overshoot, undershoot, and ringing is critical. The low output impedance of the drivers produces waveforms with high di/dt which tends to induce ringing in the parasitic inductances. Connecting the driver device close to the MOSFETs is advantageous. To reduce ringing, minimize the trace inductance from OUT 1 and OUT 2 to the MOSFET input. Connecting the PGND and AGND pins to the PowerPAD integrated circuit package with a thin trace is recommended. Ensuring that the voltage potential between these two pins does not exceed 0.3 V is critical. The use of schottky diodes on the outputs to the PGND and PVDD pins is recommended when driving gate transformers. See (3) in the 相关文档 section for a description of proper pad layout for the PowerPAD integrated circuit package.

Layout Example

UCD8220-Q1 layout_slusb36.gif Figure 40. UCD8220-Q1 Layout Example

Thermal Considerations

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCD8220-Q1 device is available in the PowerPAD integrated circuit package, HTSSOP, to cover a range of application requirements. The package has an exposed pad to enhance thermal conductivity from the semiconductor junction.

As shown in (4) in the 相关文档 section, the PowerPAD integrated circuit packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device package, reducing the RθJA down to 37.47°C/W. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as discussed in (3) in the 相关文档 section.

Note that the PowerPAD integrated circuit package is not directly connected to any leads of the package. However, the PowerPAD is electrically and thermally connected to the substrate which is the ground of the device. The PowerPAD integrated circuit package should be connected to the quiet ground of the circuit.