3V3 |
3 |
O |
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Place a 0.22-μF ceramic capacitor from this pin to analog ground. |
AGND |
5 |
— |
Analog ground return |
CLF |
7 |
O |
Current-limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output driver is forced low and the current-limit flag (CLF) is set high. The CLF signal is latched high until the device receives the next rising edge on the CLK pin. This signal is also used for the start-up handshaking between the digital controller and the analog controller |
CLK |
2 |
I |
Clock. Input pulse train contains operating frequency and maximum duty cycle limit. This pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. An internal Schmitt trigger comparator isolates the internal circuitry from any external noise. |
CS |
9 |
I |
Current sense pin. A fast current-limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting. |
CTRL |
6 |
I |
Input for the error feedback voltage from the external error amplifier. This input is multiplied by 0.5 and routed to the negative input of the PWM comparator |
ILIM |
8 |
I |
Current-limit threshold set pin. The current-limit threshold can be set to any value between 0.25 V and 1 V. The default value while open is 0.5 V. |
ISET |
4 |
I |
Pin for programming the current used to set the amount of slope compensation in peak current-mode control or to set the internal capacitor charging in voltage-mode control. |
NC |
1 |
— |
No connection. |
15 |
16 |
OUT1 |
12 |
O |
The high-current TrueDrive integrated circuit driver output. |
OUT2 |
11 |
O |
The high-current TrueDrive integrated circuit driver output. |
PGND |
10 |
— |
Power ground return. This pin should be connected close to the source of the power MOSFET. |
PVDD |
13 |
— |
Supply pin provides power for the output drivers. This pin is not connected internally to the VDD supply rail. The bypass capacitor for this pin should be returned to PGND. |
VDD |
14 |
I |
Supply input pin to power the control circuitry. Bypass the pin with a capacitor with a value of at least 4.7 μF, returned to AGND. |