ZHCSD93A january   2015  – december 2020 UCC28700-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. Pin Configuration and Functions
    1. 5.1 Pin Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-6657BD5B-29CE-4F76-A6A3-BA4B57482A18/SLUSB418335
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
        1. 7.3.1.1 VDD (Device Bias Voltage Supply)
        2. 7.3.1.2 GND (Ground)
        3. 7.3.1.3 VS (Voltage-Sense)
        4. 7.3.1.4 DRV (Gate Drive)
        5. 7.3.1.5 CS (Current Sense)
        6. 7.3.1.6 CBC (Cable Compensation)
      2. 7.3.2 Fault Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Primary-Side Voltage Regulation
      2. 7.4.2 Primary-Side Current Regulation
      3. 7.4.3 Valley-Switching
      4. 7.4.4 Start-Up Operation
  9. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Transformer Parameter Verification
        2. 8.2.2.2 Output Capacitance
        3. 8.2.2.3 VDD Capacitance, CDD
        4. 8.2.2.4 VDD Start-Up Resistance, RSTR
        5. 8.2.2.5 VS Resistor Divider, Line Compensation, and Cable Compensation
        6. 8.2.2.6 Input Bulk Capacitance and Minimum Bulk Voltage
        7. 8.2.2.7 Transformer Turns Ratio, Inductance, Primary-Peak Current
        8. 8.2.2.8 Standby Power Estimate
      3. 8.2.3 Application Curves
  10. Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1  Capacitance Terms in Farads
        2. 11.1.1.2  Duty Cycle Terms
        3. 11.1.1.3  Frequency Terms in Hertz
        4. 11.1.1.4  Current Terms in Amperes
        5. 11.1.1.5  Current and Voltage Scaling Terms
        6. 11.1.1.6  Transformer Terms
        7. 11.1.1.7  Power Terms in Watts
        8. 11.1.1.8  Resistance Terms in Ω
        9. 11.1.1.9  Timing Terms in Seconds
        10. 11.1.1.10 Voltage Terms in Volts
        11. 11.1.1.11 AC Voltage Terms in VRMS
        12. 11.1.1.12 Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Trademarks
  13.   Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Layout Guidelines

  • High frequency bypass Capacitor C7 should be placed arcos Pin 2 and 5 as close as you can get it to the pins.
  • Resistor R15 and C7 form a low pass filter and the connection of R15 and C7 should be as close to the VDD pin as possible.
  • C9 should be put as close to CS pin and R10 as possible. This forms a low pass filter with R10.
  • The connection for C9 and R10 should be as close to the CS pin as possible.
  • Please note that C9 may not be required in all designs. However, it is wise to put a place holder for it in your design.
  • The VS pin controls the output voltage through the transformer turns ratio and the voltage divider of R7 and R9. Note the trace with between the R7, R9 and VS pin should be; as short as; possible to reduce/eliminate possible EMI coupling.
  • Note the IC ground and power ground should meet at the bulk capacitor’s (C4 and C5) return. Tri to ensure that high frequency/high current from the power stage does not go through the signal ground.
    • The high frequency/high current path that you need to be cautious of on the primary is C4, C5 +, T1 (P1,P2), Q1d, Q1s, R13 to the return of C4 and C5.
  • Try to keep all high current loops as short as possible.
  • Keep all high current/high frequency traces away from or perpendicular to other traces in the design.
  • Traces on the voltage clamp formed by D1, R1, D4 and C4 as short as possible.
  • C4 return needs to be as close to the bulk capacitor supply as possible. This reduces the magnitude of dv/dt caused by large di/dt.
  • Avoid mounting semiconductors under magnetics.

GUID-1B30AEEB-EC84-4D15-A588-B0A81B1C93DE-low.gifFigure 10-1 5-W USB Adapter Schematic