ZHCSKL2A December   2019  – May 2022 TUSS4470

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power-Up Characteristics
    6. 6.6  Transducer Drive
    7. 6.7  Receiver Characteristics
    8. 6.8  Echo Interrupt Comparator Characteristics
    9. 6.9  Digital I/O Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excitation Power Supply (VDRV)
      2. 7.3.2 Burst Generation
        1. 7.3.2.1 Burst Generation Diagnostics
      3. 7.3.3 Direct Transducer Drive
      4. 7.3.4 Analog Front End
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 REG_USER Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Transducer Drive Configuration Options
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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Programming

The primary communication between the IC and the external MCU is through an SPI bus that provides full-duplex communications in a controller-peripheral configuration. The external MCU is always a SPI controller that sends command requests on the SDI pin and receives device responses on the SDO pin. The device is always a SPI peripheral device that receives command requests and sends responses to the external MCU over the SDO line. The following lists the characteristics of the SPI:

  • The SPI is a 4-pin interface.
  • The frame size is 16 bits and is assigned as follows:
      Controller-to-peripheral (MCU to TUSS4470 over the SDI line)1 RW bit, 6 bits for the register address, 1 ODD parity bit for entire SPI frame, 8 bits for data
      Peripheral-to-controller (TUSS4470 to MCU over the SDO line)1 bit for Controller Parity error reporting during previous frame reception, 6 bits for the status, 1 bit for ODD parity for entire SPI frame, 8 bits for data
  • SPI commands and data are shifted with the MSB first and the LSB last.
  • The SDO line is sampled on the falling edge of the SCLK pin.
  • The SDI line is shifted out on the rising edge of the SCLK pin.

The SPI communication begins with the NCS falling edge and ends with the NCS rising edge. The NCS high-level maintains the SPI peripheral-interface in the RESET state. The SDO output is in the tri-state condition.

The SPI does not support back-to-back SPI frame operation. After each SPI transfer the NCS pin must go from low to high before the next SPI transfer can begin.

Figure 7-9 shows an overview of a complete 16-bit SPI frame.



Figure 7-9 16-Bit SPI Frame

Figure 7-10 shows a SPI transfer sequence between the controller and the peripheral TUSS4470 device. When the controller is writing a SPI frame, the parity error bit indicates if there was a parity error for the previous frame. When the controller is transmitting the data for the SPI write, the peripheral echoes back register address that was sent just before in the command.



Figure 7-10 SPI Transfer Sequence

The status bits are defined in Table 7-4:

Table 7-4 SPI Interface Status Bits Description
STATUS BITDESCRIPTION
STAT 5 - VDRV_READYSet when VDRV power regulator has reached the programmed voltage level. This is also indicated by VDRV_READY bit.
STAT 4- PULSE_NUM_FLTSet if the burst sequence was terminated before completing the pulse number selected. This is also indicated by PULSE_NUM_FLT bit.
STAT 3 - DRV_PULSE_FLTSet if there is a "stuck" fault detected during pulsing in a burst sequence. This is also indicated by DRV_PULSE_FLT
STAT 2 - EE_CRC_FLTSet if there is a CRC Error when loading internal EEPROM memory. This is also indicated by EE_CRC_FLT bit.
STAT <1:0> - DEV_STATEDevice State:
00 - LISTEN
01 - BURST
10 - STANDBY
11 - SLEEP