ZHCSKL2A December   2019  – May 2022 TUSS4470

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power-Up Characteristics
    6. 6.6  Transducer Drive
    7. 6.7  Receiver Characteristics
    8. 6.8  Echo Interrupt Comparator Characteristics
    9. 6.9  Digital I/O Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Excitation Power Supply (VDRV)
      2. 7.3.2 Burst Generation
        1. 7.3.2.1 Burst Generation Diagnostics
      3. 7.3.3 Direct Transducer Drive
      4. 7.3.4 Analog Front End
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 REG_USER Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Transducer Drive Configuration Options
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Transducer Driving Voltage
          2. 8.2.1.2.2 Transducer Driving Frequency
          3. 8.2.1.2.3 Transducer Pulse Count
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

Analog Front End

GUID-B9D213D3-55E6-4ECC-AEA7-82F8A55DDBE8-low.gifFigure 7-7 TUSS4470 Analog Front-End Block Diagram

Figure 7-7 shows the analog front-end block diagram that can receive and condition the signals from the transducer during listen mode. The received echo is first amplified with a fixed linear low-noise amplifier, followed by either a bandpass filter or a high-pass filter to remove noise out of the expected signal band. After filtering the signal, the signal is fed into a logarithmic amplifier. The output of the logarithmic amplifier is then buffered to the VOUT pin. In Figure 7-7, every block has the register name associated with it that can be used to configure the signal path. The final equation for the signal path is given by Equation 2:

Equation 1. GUID-F27CFAB9-FB7E-46F5-8C1A-CCE7CE9311A2-low.gif

where

The bandpass filter is critical for reducing noise to allow utilization of the complete dynamic range of the logarithmic amplifier. The center frequency of the bandpass filter can be configured to be close the transducer frequency which is set by the BPF_HPF_FREQ bits. Table 7-1 shows the nominal values for the BPF center frequency corresponding to the BPF_HPF_FREQ register value. The TUSS4470 supports a wide range of frequencies, therefore a factory trim is used to remove process variation for a particular pre-determined frequency. It is possible that all other frequencies listed in Table 7-1 do not correspond exactly to value of BPF_HPF_FREQ in a factory trim. The user can vary the value of the BPF_HPF_FREQ register around the desired center frequency while actively bursting and observing the VOUT signal. The value with maximum voltage at VOUT pin will the desired setting for the BPF_HPF_FREQ register.

Table 7-1 Bandpass Filter Center Frequency Configuration
BPF_HPF_FREQ (HEX)
(BPF_FC_TRIM_FRC = 0)
BPF_Fc (KHz)
0x0040.64
0x0144.05
0x0245.6
0x0348.86
0x0450.58
0x0552.96
0x0656.75
0x0760.11
0x0862.95
0x0966.68
0x0A71.44
0x0B74.81
0x0C79.24
0x0D82.03
0x0E86.89
0x0F92.04
0x1097.49
0x11103.27
0x12109.4
0x13114.54
0x14121.33
0x15128.52
0x16134.58
0x17142.55
0x18151.01
0x19159.94
0x1A167.48
0x1B177.41
0x1C185.77
0x1D196.78
0x1E206.05
0x1F218.26
0x20228.54
0x21244.89
0x22256.43
0x23271.63
0x24284.43
0x25301.28
0x26319.13
0x27338.14
0x28353.97
0x29374.95
0x2A397.16
0x2B408.17
0x2C420.7
0x2D455.63
0x2E472.03
0x2F500

The factory trim can be overridden by setting the BPF_FC_TRIM_FRC bit first and varying the BPF_FC_TRIM bit after. This is useful in two ways:

  • If the factory trimmed bandpass filter center frequency is higher than the desired value for BPF_HPF_FREQ = 0x00, or lower than desired value for BPF_HPF_FREQ = 0x2F, then BPF_FC_TRIM can be used to recover the range.
  • This setting can also be used to extend the frequency range of the bandpass filter center frequency.
The BPF_FC_TRIM acts like an offset on top of the BPF_HPF_FREQ setting. Table 7-2 shows the nominal value of center frequency when this offset is added to the minimum and maximum BPF_HPF_FREQ code. Figure 6-11 shows the measured data. For BPF_HPF_FREQ values greater than 0x08 and less than 0x27, varying BPF_FC_TRIM keeping BPF_HPF_FREQ fixed is the same as setting BPF_FC_TRIM = 0x00 and varying BPF_HPF_FREQ to find the optimum setting.

Table 7-2 Bandpass Filter Center Frequency Range Extension
BPF_HPF_FREQ (hex) + BPF_FC_TRIM (hex)
(BPF_FC_TRIM_FRC = 1)
BPF_Fc (KHz)
0x00 + 0x827.48
0x00 + 0x929.44
0x00 + 0xA30.83
0x00 + 0xB31.19
0x00 + 0xC32.65
0x00 + 0xD34.19
0x00 + 0xE35.8
0x00 + 0xF38.81
0x2F + 0x1523.56
0x2F + 0x2554.59
0x2F + 0x3587.45
0x2F + 0x4622.23
0x2F + 0x5651.58
0x2F + 0x6690.19
0x2F + 0x7731.09
Note:

The logamp provides compression for large signal inputs and amplifies linearly small signal inputs. Logamp simplifies system design to detect varying strengths of echoes that happens because of difference in reflectivity of different types of objects and objects at different distances. It automatically adjusts its gain based on the input signal level. The logamp also demodulates the incoming signal.

The logamp consists of multiple gain stages and range extension stages that are combined to give a logarithmic response. The current consumption of the device can be reduced by turning off the either the first stage, the last stage of the logamp, or both, by setting the LOGAMP_DIS_FIRST and LOGAMP_DIS_LAST bits. Disabling the stages will reduce the input dynamic range on the lower side of the range (see Figure 6-4). The pedestal noise floor will be lower because the gain stages are disabled, but the minimum detectable signal value becomes higher due to the reduced dynamic range. Depending on the received input signal strength, stages can be disabled to get optimum object detection. For very small inputs, all stages should be enabled to get maximum input dynamic range even though the noise floor is higher. Figure 6-6, Figure 6-7, and Figure 6-8 show the effect on the log conformance error when all stages are enabled, when the last stage is disabled, and when both first and last stages are disabled. When stages are disabled, a lower error is obtained with a lower noise floor, but the input dynamic range is reduced.

At the output of the logamp, the user can apply an adjustment to the intercept of the logamp curve. This is denoted by the KX factor in Equation 1. The intercept adjustment is controlled by the LOGAMP_INT_ADJ bits. Table 7-3 shows the nominal values of KX factor corresponding to register values, and Figure 6-14 shows its effect on the transfer function.

Table 7-3 Logamp Intercept Adjustment
LOGAMP_INT_ADJKX
0x001
0x011.155
0x021.334
0x031.54
0x041.778
0x052.054
0x062.371
0x072.738
0x081
0x090.931
0x0A0.866
0x0B0.806
0x0C0.75
0x0D0.698
0x0E0.649
0x0F0.604

The output of the logamp is filtered using a low-pass filter to remove the high-frequency components and provide a sufficient peak hold time for the demodulated envelope signal. The cut-off frequency of the low-pass filter is set by the internal impedance of the FLT pin and the value of an external capacitor connected to the pin. As this filter capacitance (CFLT) suppresses the high frequency fluctuations, it also slows down the response time of the logamp. Higher CFLT capacitance will result in lower peak-to-peak voltage variations at VOUT, and slower rise and fall times for the VOUT voltage to reach its maximum value for a given input signal. A nominal value can be calculated using Equation 3, and must be optimized depending on the application.

The output of the low-pass filter is buffered to the VOUT pin using an internal buffer. The buffer is designed to support an ADC input of a MCU. It is possible to change output dynamic range of the VOUT buffer using the VOUT_SCALE_SEL bit. Once the range is set, the gain of the VOUT buffer can be set by the LOGAMP_SLOPE_ADJ bits. The slope variation of the receiver analog front end is show in Figure 6-13.

Echo interrupt signal is available on the OUT4 pin that goes high when the signal on the VOUT pin crosses a threshold as defined by the ECHO_INT_THR_SEL bits. As long as the VOUT signal is higher than this threshold, the echo interrupt signal is held high. The signal goes low asynchronously when the VOUT signal drops below the programmed threshold. This signal can be used to interrupt a MCU when an object has been detected. The threshold value is also dependent on the setting of the VOUT_SCALE_SEL bit.

A zero-crossing signal is output at the OUT3 pin which can be used to validate the frequency of the received echo signal to provide robustness against interference from other signals. This zero-crossing signal is derived from the raw amplified input signal from a particular stage as it is being demodulated in the logamp block. This function is disabled at device power up. but can be enabled by setting the ZC_CMP_EN bit. When enabled, the ZC_CMP_STG_SEL bits are used to select which logamp gain stage is used to generate the zero crossing signal while the ZC_CMP_HYST bits control the hysteresis of the zero-crossing comparator. The stage selection to see the OUT3 pin toggling depends on the strength of signal received by the logamp and has to be configured depending on the application. For large amplitude of input signal, a lower stage of the logamp should be selected, whereas for lower amplitude signal, a higher stage should be selected. To avoid switching noise generated by the toggling of the zero-crossing comparator when the ZC_EN_ECHO_INT bit is set, the zero-crossing output will be only enabled while the echo interrupt signal is high.