ZHCSI26C August   2010  – April 2018 TPS54320

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      效率与负载电流间的关系
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Current Mode Operation (CCM)
      3. 7.3.3  VIN and Power VIN Pins (VIN and PVIN)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Adjusting the Output Voltage
      6. 7.3.6  Safe Start-up into Prebiased Outputs
      7. 7.3.7  Error Amplifier
      8. 7.3.8  Slope Compensation
      9. 7.3.9  Enable and Adjusting UVLO
      10. 7.3.10 Slow Start (SS/TR)
      11. 7.3.11 Power Good (PWRGD)
      12. 7.3.12 Bootstrap Voltage (BOOT) and Low Dropout Operation
      13. 7.3.13 Sequencing (SS/TR)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-Side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-Side MOSFET Overcurrent Protection
      16. 7.3.16 Thermal Shutdown
      17. 7.3.17 Small Signal Model for Loop Response
      18. 7.3.18 Simple Small Signal Model for Peak Current Mode Control
      19. 7.3.19 Small Signal Model for Frequency Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Adjustable Switching Frequency and Synchronization (RT/CLK)
      2. 7.4.2 Adjustable Switching Frequency (RT Mode)
      3. 7.4.3 Synchronization (CLK Mode)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Operating Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor Selection
        5. 8.2.2.5  Input Capacitor Selection
        6. 8.2.2.6  Slow-Start Capacitor Selection
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  UVLO Set Point
        9. 8.2.2.9  Output Voltage Feedback Resistor Selection
          1. 8.2.2.9.1 Minimum Output Voltage
        10. 8.2.2.10 Compensation Component Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 使用 WEBENCH® 工具创建定制设计
    2. 11.2 文档支持
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS54320 UNIT
VQFN
14 PINS
RθJA Junction-to-ambient thermal resistance 42.8 °C/W
RθJA Junction-to-ambient thermal resistance(3) 32 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.4 °C/W
RθJB Junction-to-board thermal resistance 15.9 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 15.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more information.
(3) Test board conditions:
  1. 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
  2. 2-oz. copper traces located on the top of the PCB
  3. 2-oz. copper ground planes on the 2 internal layers and bottom layer
  4. 40.010-inch thermal vias located under the device package