Table 1. Design Parameters

9.2.2.1 Choose Inductor

The inductance value is selected to provide approximately 30% peak to peak ripple current at maximum load. Larger ripple current increases output ripple voltage, improve S/N ratio and contribute to stable operation. L1 can be calculated using Equation 3.

Equation 3.

The inductors current ratings needs to support both the RMS (thermal) current and the peak (saturation) current. The RMS and peak inductor current can be estimated as follows:

Equation 4.

Equation 5.

Equation 6.

Note:

The calculation above shall serve as a general reference. To further improve transient response, the output inductance could be reduced further. This needs to be considered along with the selection of the output capacitor.

9.2.2.2 Choose Output Capacitor

The capacitor value and ESR determines the amount of output voltage ripple and load transient response. Recommend to use ceramic output capacitor.

Equation 7.

Equation 8.

Where:

Equation 9.

Equation 10.

Select the capacitance value greater than the largest value calculated from Equation 7, Equation 8 and Equation 10. The capacitance for C1 should be greater than 66 μF.

Where:

Δ V_OS = The allowable amount of overshoot voltage in load transition

ΔV_US = The allowable amount of undershoot voltage in load transition

T_min(off) = Minimum off time

9.2.2.3 Choose Input Capacitor

The TPS53114 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A minimum 10-μF high-quality ceramic capacitor is recommended for the input capacitor. The capacitor voltage rating needs to be greater than the maximum input voltage.

9.2.2.4 Choose Bootstrap Capacitor

The TPS53114 requires a bootstrap capacitor from SW to VBST to provide the floating supply for the high-side drivers. A minimum 0.1-μF high-quality ceramic capacitor is recommended. The voltage rating should be greater than 10.0 V.

9.2.2.5 Choose VREG5 and V5FILT Capacitors

The TPS53114 requires both the VREG5 regulator and V5FILT input are bypassed. A minimum 4.7-μF high-quality ceramic capacitor must be connected between the VREG5 and GND for proper operation. A minimum 1.0-μF high-quality ceramic capacitor must be connected between the V5FILT and GND for proper operation. Both of these capacitors' voltage ratings should be greater than 10 V.

9.2.2.6 Choose Output Voltage Set Point Resistors

The output voltage is set with a resistor divider from output voltage node to the VFBx pin. It is recommended to use 1% tolerance or better resistors. Select R2 between 10 kΩ and 100 kΩ and use Equation 11 or Equation 12 to calculate R1.

Equation 11.

Equation 12.

Where:

VFB1_(ripple) = Ripple voltage at VFB1

9.2.2.7 Choose Over Current Set Point Resistor

Equation 13.

Equation 14.

Where:

R_DS(ON) = Low side FET on-resistance

I_TRIP = TRIP pin source current （≉ 10 μA）

V_OCLoff = Minimum over current limit offset voltage (-20 mV)

I_OCL = over current limit

9.2.2.8 Choose Soft Start Capacitor

Soft start timing equations are as follows:

Equation 15.

Equation 16.

9.2.2.9 Choose Package Option

TPS53114 power dissipation:

Equation 17.

Where:

C_iH = Input capacitor of high side MOSFET

C_iL = Input capacitor of low side MOSFET

Choose package considering the Dissipation Rating table.

Table 2. Design Parameters