ZHCSF57 June   2016 TPS51200-EP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Sink and Source Regulator (VO Pin)
      2. 7.3.2  Reference Input (REFIN Pin)
      3. 7.3.3  Reference Output (REFOUT Pin)
      4. 7.3.4  Soft-Start Sequencing
      5. 7.3.5  Enable Control (EN Pin)
      6. 7.3.6  Powergood Function (PGOOD Pin)
      7. 7.3.7  Current Protection (VO Pin)
      8. 7.3.8  UVLO Protection (VIN Pin)
      9. 7.3.9  Thermal Shutdown
      10. 7.3.10 Tracking Start-up and Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low-Input Voltage Applications
      2. 7.4.2 S3 and Pseudo-S5 Support
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical VTT DIMM Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Voltage Capacitor
        2. 8.2.2.2 VLDO Input Capacitor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Output Tolerance Consideration for VTT DIMM Applications
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 3.3-VIN, DDR2 Configuration
      2. 8.3.2 2.5-VIN, DDR3 Configuration
      3. 8.3.3 3.3-VIN, LP DDR3 or DDR4 Configuration
      4. 8.3.4 3.3-VIN, DDR3 Tracking Configuration
      5. 8.3.5 3.3-VIN, LDO Configuration
      6. 8.3.6 3.3-VIN, DDR3 Configuration with LFP
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Design Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 开发支持
        1. 11.1.2.1 评估模块
        2. 11.1.2.2 Spice 模型
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Input voltage(2) REFIN, VIN, VLDOIN, VOSNS –0.3 3.6 V
EN –0.3 6.5
PGND to GND –0.3 0.3
Output voltage(2) REFOUT, VO –0.3 3.6 V
PGOOD –0.3 6.5
Operating junction temperature, TJ –55 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltages VIN 2.375 3.5 V
Voltage EN, VLDOIN, VOSNS –0.1 3.5 V
REFIN 0.5 1.8
PGOOD, VO –0.1 3.5
REFOUT –0.1 1.8
PGND –0.1 0.1
Operating junction temperature, TJ –55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS51200-EP UNIT
DRC (VSON)
10 PINS
RθJA Junction-to-ambient thermal resistance 55.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 84.6 °C/W
RθJB Junction-to-board thermal resistance 30 °C/W
ψJT Junction-to-top characterization parameter 5.5 °C/W
ψJB Junction-to-board characterization parameter 30.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 10.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over recommended junction temperature range, VVIN = 3.3 V, VVLDOIN = 1.8 V, VREFIN = 0.9 V, VVOSNS = 0.9 V, VEN = VVIN, COUT = 3 × 10 μF and circuit shown in (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IIN Supply current TJ = 25 °C, VEN = 3.3 V, no load 0.7 1 mA
IIN(SDN) Shutdown current TJ = 25 °C, VEN = 0 V, VREFIN = 0,
no load		 65 80 μA
TJ = 25 °C, VEN = 0 V, VREFIN > 0.4 V, no load 200 400
ILDOIN Supply current of VLDOIN TJ = 25 °C, VEN = 3.3 V, no load 1 50 μA
ILDOIN(SDN) Shutdown current of VLDOIN TJ = 25 °C, VEN = 0 V, no load 0.1 50 μA
INPUT CURRENT
IREFIN Input current, REFIN VEN = 3.3 V 1 μA
VO OUTPUT
VVOSNS Output DC voltage, VO VREFOUT = 1.25 V (DDR1), IO = 0 A 1.25 V
–15 15 mV
VREFOUT = 0.9 V (DDR2), IO = 0 A 0.9 V
–15 15 mV
VLDOIN = 1.5 V, VREFOUT = 0.75 V (DDR3), IO = 0 A 0.75 V
–15 15 mV
VVOTOL Output voltage tolerance to REFOUT –2 A < IVO < 2 A –25 25 mV
IVOSRCL VO source current Limit With reference to REFOUT,
VOSNS = 90% × VREFOUT 		3 4.5 A
IVOSNCL VO sink current Limit With reference to REFOUT,
VOSNS = 110% × VREFOUT 		3.5 5.5 A
IDSCHRG Discharge current, VO VREFIN = 0 V, VVO = 0.3 V, VEN = 0 V, TJ = 25°C 18 25 Ω
POWERGOOD COMPARATOR
VTH(PG) VO PGOOD threshold PGOOD window lower threshold with respect to REFOUT –23.5% –20% –17.5%
PGOOD window upper threshold with respect to REFOUT 17.5% 20% 23.5%
PGOOD hysteresis 5%
tPGSTUPDLY PGOOD start-up delay Start-up rising edge, VOSNS within 15% of REFOUT 2 ms
VPGOODLOW Output low voltage ISINK = 4 mA 0.4 V
tPBADDLY PGOOD bad delay VOSNS is outside of the ±20% PGOOD window 10 μs
IPGOODLK Leakage current(1) VOSNS = VREFIN (PGOOD high impedance), VPGOOD = VVIN + 0.2 V 1 μA
REFIN AND REFOUT
VREFIN REFIN voltage range 0.5 1.8 V
VREFINUVLO REFIN undervoltage lockout REFIN rising 360 390 420 mV
VREFINUVHYS REFIN undervoltage lockout hysteresis 20 mV
VREFOUT REFOUT voltage REFIN V
VREFOUTTOL REFOUT voltage tolerance to VREFIN –10 mA < IREFOUT < 10 mA,
VREFIN = 1.25 V		 –15 15 mV
–10 mA < IREFOUT < 10 mA,
VVREFIN = 0.9 V		 –15 15
–10 mA < IREFOUT < 10 mA,
VREFIN = 0.75 V		 –15 15
–10 mA < IREFOUT < 10 mA,
VREFIN = 0.6 V		 –15 15
IREFOUTSRCL REFOUT source current limit VREFOUT = 0 V 10 40 mA
IREFOUTSNCL REFOUT sink current limit VREFOUT = 0 V 10 40 mA
UVLO AND EN LOGIC THRESHOLD
VVINUVVIN UVLO threshold Wake up, TJ = 25°C 2.2 2.3 2.375 V
Hysteresis 50 mV
VENIH High-level input voltage Enable 1.7 V
VENIL Low-level input voltage Enable 0.3 V
VENYST Hysteresis voltage Enable 0.5 V
IENLEAK Logic input leakage current EN, TJ = 25°C –1 1 μA
THERMAL SHUTDOWN
TSON Thermal shutdown threshold(1) Shutdown temperature 150 °C
Hysteresis 25
(1) Ensured by design. Not production tested.
TPS51200-EP D013_SLUSA48.gif
1. Electromigration fail mode = time at temperature with bias.
2. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life).
3. The predicted operating lifetime versus junction temperature is based on reliability modeling and available qualification data.
Figure 1. Predicted Lifetime Derating Chart for TPS51200-EP

6.6 Typical Characteristics

3 × 10-µF MLCCs (0805) are used on the output.
TPS51200-EP D001_SLUSA48.gif
VVIN = 3.3 V DDR
Figure 2. Load Regulation
TPS51200-EP D003_SLUSA48.gif
VVIN = 3.3 V DDR3
Figure 4. Load Regulation
TPS51200-EP D005_SLUSA48.gif
VVIN = 2.5 V DDR
Figure 6. Load Regulation
TPS51200-EP D007_SLUSA48.gif
VVIN = 2.5 V DDR3
Figure 8. Load Regulation
TPS51200-EP D009_SLUSA48.gif
DDR
Figure 10. REFOUT Load Regulation
TPS51200-EP D011_SLUSA48.gif
DDR3
Figure 12. REFOUT Load Regulation
TPS51200-EP droupout_reg_slus812.gif
Figure 14. DROPOUT Voltage vs Output Current
TPS51200-EP bode_ddr3_slus812.gif
DDR3
Figure 16. Bode Plot
TPS51200-EP D002_SLUSA48.gif
VVIN = 3.3 V DDR2
Figure 3. Load Regulation
TPS51200-EP D004_SLUSA48.gif
VVIN = 3.3 V LP DDR3 or DDR4
Figure 5. Load Regulation
TPS51200-EP D006_SLUSA48.gif
VVIN = 2.5 V DDR2
Figure 7. Load Regulation
TPS51200-EP D008_SLUSA48.gif
VVIN = 2.5 V LP DDR3 or DDR4
Figure 9. Load Regulation
TPS51200-EP D010_SLUSA48.gif
DDR2
Figure 11. REFOUT Load Regulation
TPS51200-EP D012_SLUSA48.gif
LP DDR3 or DDR4
Figure 13. REFOUT Load Regulation
TPS51200-EP bode_ddr2_slus812.gif
DDR2
Figure 15. Bode Plot