ZHCSBP7C October   2013  – December 2018 TPS24750 , TPS24751

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      应用原理图 (12V/10A)
      2.      瞬态输出短路响应
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Descriptions
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  DRAIN
      2. 9.3.2  EN
      3. 9.3.3  FLTb
      4. 9.3.4  GATE
      5. 9.3.5  GND
      6. 9.3.6  IMON
      7. 9.3.7  OUT
      8. 9.3.8  OV
      9. 9.3.9  PGb
      10. 9.3.10 PROG
      11. 9.3.11 SENSE
      12. 9.3.12 TIMER
      13. 9.3.13 VCC
    4. 9.4 Device Functional Modes
      1. 9.4.1 Board Plug-In
      2. 9.4.2 Inrush Operation
      3. 9.4.3 Action of the Constant-Power Engine
      4. 9.4.4 Circuit Breaker and Fast Trip
      5. 9.4.5 Automatic Restart
      6. 9.4.6 Start-Up with Short on Output
      7. 9.4.7 PGb, FLTb, and Timer Operations
        1. 9.4.7.1 Overtemperature Shutdown
        2. 9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power-Limited Start-Up
          1. 10.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
          2. 10.2.2.1.2 STEP 2. Choose Power-Limit Value, PLIM, and RPROG
          3. 10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
          4. 10.2.2.1.4 STEP 4. Calculate the Retry-Mode Duty Ratio
          5. 10.2.2.1.5 STEP 5. Select R1, R2, and R3 for UV and OV
          6. 10.2.2.1.6 STEP 6. Choose R4, R5, and C1
        2. 10.2.2.2 Alternative Design Example: Gate Capacitor (dv/dt) Control in Inrush Mode
        3. 10.2.2.3 Additional Design Considerations
          1. 10.2.2.3.1 Use of PGb
          2. 10.2.2.3.2 Output Clamp Diode
          3. 10.2.2.3.3 Gate Clamp Diode
          4. 10.2.2.3.4 Bypass Capacitors
          5. 10.2.2.3.5 Output Short-Circuit Measurements
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 Transient Thermal Impedance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 Export Control Notice
    8. 13.8 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

PGb, FLTb, and Timer Operations

The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across internal FET. PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is still charging. PGb goes active-low about 3.4 ms after COUT is charged. This delay allows the internal FET to fully turnon and any transients in the power circuits to end before the converter starts up. This type of sequencing prevents the downstream converter from demanding full current before the power-limiting engine allows the internal FET to conduct the full current set by the current limit ILIM. Failure to observe this precaution may prevent the system from starting. The pullup resistor shown on the PGb pin in the typical system block diagram application diagram Figure 41 is illustrative only; the actual connection to the converter depends on the application. The PGb pin may indicate that inrush has ended before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its full operating voltage. After the hot-swap circuit successfully starts up, the PGb pin can return to a high-impedance status whenever the drain-to-source voltage of internal FET exceeds its upper threshold of 340 mV, which presents the downstream converters a warning flag. This flag may occur as a result of overload fault, output short fault, input overvoltage, higher die temperature, or the GATE shutdown by UVLO, EN.

FLTb is an indicator that the allowed fault-timer period during which the load current can exceed the programmed current limit (but not the fast-trip threshold) expires. The fault timer starts when a current of approximately 10 μA begins to flow into the external capacitor CT, and ends when the voltage of CT reaches TIMER upper threshold, that is, 1.35 V. FLTb pulls low at the end of the fault timer. Otherwise, FLTb assumes a high-impedance state.

The fault-timer state requires an external capacitor CT connected between the TIMER pin and GND pin. The duration of the fault timer is the charging time of CT from 0 V to its upper threshold of 1.35 V. The fault timer begins to count under any of the following three conditions:

  1. In the inrush mode, TIMER begins to source current to the timer capacitor, CT, when device is enabled. TIMER begins to sink current from the timer capacitor, CT when V(GATE – VCC) exceeds the timer activation voltage (see the Inrush Operation section). If V(GATE – VCC) does not reach the timer activation voltage before TIMER reaches 1.35 V, then the TPS2475x disables the internal FET. After the MOSFET turns off, the timer goes into either latch mode (TPS24750) or retry mode (TPS24751).
  2. In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24750) or retry mode (TPS24751).
  3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, CT, when the load current exceeds the programmed current limits following a fast-trip shutdown of internal FET. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24750) or retry mode (TPS24751).

If the fault current drops below the programmed current limit within the fault timer period, VTIMER decreases and the internal pass MOSFET remains enabled.

The behaviors of TIMER are different in the latch mode and retry mode. If the timer capacitor reaches the upper threshold of 1.35 V, then:

  • In latch mode(TPS24750), the TIMER pin continues to charge and discharge the attached capacitor periodically until device is disabled by UVLO, EN, or OV, as shown in Figure 38.
  • In retry mode(TPS24751), TIMER charges and discharges CT between the lower threshold of 0.35 V and the upper threshold of 1.35 V for sixteen cycles before the device attempts to re-start. The TIMER pin is pulled to GND at the end of the 16th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is removed or the TPS2475x is disabled by UVLO, EN or OV.