8.3.1 Port Remapping

The TPS2388 provides port remapping capability, from the logical ports to the physical ports/pins.

The remapping is between any port of a 4-port group (1 to 4, 5 to 8).

The following example is applicable to 0x26 register = 00111001, 00111001b.

• Logical port 1 (5) ↔ Physical port 2 (6)
• Logical port 2 (6) ↔ Physical port 3 (7)
• Logical port 3 (7) ↔ Physical port 4 (8)
• Logical port 4 (8) ↔ Physical port 1 (5)

If the TPS2388 receives an incorrect configuration, it simply ignores the incorrect configuration and keeps the configuration unchanged. The ACK is also sent as usual at the end of communication. For example, if the same code is received for more than one port, then a read back of the Re-Mapping register (0x26) would be the last valid configuration.

Also note that if an IC reset command (1Ah register) is received, the port remapping configuration is kept unchanged. However, if there is a Power-on Reset or if the RESET pin is activated, the Re-Mapping register is reinitialized to a default value.

8.3.2 Port Power Priority

The TPS2388 supports 1- and 3-bit shutdown priority, selectable with the MbitPrty bit of General Mask register (0x17).

The 1-bit shutdown priority works with the Port Power Priority (0x15) register. An OSSn bit with a value of 1 indicates that the corresponding port will be treated as low priority, while a value of 0 corresponds to a high priority. As soon as the OSS input goes high, the low-priority ports are turned off.

The 3-bit shutdown priority works with the Multi Bit Power Priority (0x27/28) register, which holds the priority settings. A port with “000” code in this register has highest priority. Port priority reduces as the 3-bit value increases, with up to 8 priority levels. See Figure 16.

The port priority is defined as the following:

• OSS code ≤ Priority setting (0x27/28 register): OSS code turns off the port
• OSS code > Priority setting (0x27/28 register): OSS code has no impact on the port

Figure 16. Multi-Bit Priority Port Shutdown if Lower-Priority Port

8.3.3 A/D Converter

The TPS2388 features ten multi-slope integrating converters. Each of the first eight converters is dedicated to current measurement for one port and is operated independently to perform measurements in any of the following modes: classification and port powered. When the port is powered, the converter is used for current (100-ms averaged) monitoring, port policing, and DC disconnect. Each of the last two converters are shared within a group of four ports for discovery (16.6-ms averaged), port powered voltage monitoring, Power Good status, and FET short detection. It is also used for general-purpose measurements including input voltage (1 ms) and temperature.

The A/D converter type used in the TPS2388 differs from other similar types of converters in that it converts while the input signal is being sampled by the integrator, providing inherent filtering over the conversion period. The typical conversion time of the current converters is 800 µs, while it is 1 ms for the other converters. Powered-device detection is performed by averaging 16 consecutive samples providing significant rejection of noise at 50-Hz or 60-Hz line frequency. While a port is powered, digital averaging is used to provide a port current measurement integrated over a 100-ms time period. Note also that an anti-aliasing filter is present for port powered current monitoring.

8.3.4 I²C Watchdog

An I²C Watchdog timer is available on the TPS2388 device. The timer monitors the I²C, SCL line for clock edges. When enabled, a timeout of the watchdog resets the I²C interface along with any active ports. This feature provides protection in the event of a hung software situation or I²C bus hang-up by slave devices. In the latter case, if a slave is attempting to send a data bit of 0 when the master stops sending clocks, then the slave could get stuck driving the data line low indefinitely. Because the data line is being driven low, the master cannot send a STOP to clean up the bus. Activating the I²C watchdog feature of the TPS2388 would clear this deadlocked condition. If the timer of 2 seconds expires, the ports latch off and the WD Status bit is set. Note that WD Status will be set even if the watchdog is not enabled. WD Status can only be cleared by a reset or writing a 0 to the WDS status bit location. The 4-bit watchdog disable field shuts down this feature when a code of 1011b is loaded. This field is preset to 1011b whenever the TPS2388 is initially powered. Also see I2C WATCHDOG Register for more details.

8.3.5 Foldback Protection

The TPS2388 features two types of foldback protection mechanisms for complete MOSFET protection. During inrush at port turn on, the foldback is based on the port voltage as shown in Figure 17. Note that the inrush current profile remains the same, whatever the state of the PoEPn bit in the PoE Plus register.

After the port has been turned on and the Power Good is valid, a dual-slope foldback is used, providing protection against partial and total short-circuit at port output, while still being able to maintain the PD powered during normal transients at the PSE input voltage. Note that setting the PoEPn bit selects the 2× curve and clearing it selects the 1× curve. See Figure 18.

Figure 17. Foldback during Inrush (at Port Turn On): I_LIM vs V_port

Figure 18. Foldback when the Port is Already ON: I_LIM vs V_drain

8.4.1 Port Operating Modes

8.4.2 Detection

To eliminate the possibility of false detection, the TPS2388 uses a TI proprietary 4-point detection method to determine the signature resistance of the PD device. False detection of a 25-kΩ signature can occur with 2-point detection type PSEs in noisy environments or if the load is highly capacitive.

Both detection 1 and detection 2 are merged into a single detection function which is repeated. Detection 1 applies I1 (160 μA) to a port, waits 60 ms, then measures the port voltage V1 with the integrating ADC. Detection 2 applies I2 (270 μA) to a port, waits 60 ms, then measures the port voltage V2. The process is repeated a second time. Multiple comparisons and calculations are performed on all four measurement point combinations to eliminate the effects of a non-linear or hysteretic PD signature. The resulting port signature is then sorted into the appropriate category.

8.4.3 Classification

Hardware classification (class) is performed by supplying a voltage and sampling the resulting current. To eliminate the high power of a classification event from occurring in the power controller chip, the TPS2388 makes use of the external power FET for classification.

During classification, the voltage on the gate node of the external MOSFET is part of a linear control loop. The control loop applies the appropriate MOSFET drive to maintain a differential voltage between VPWR and DRAIN of 17.5 V. During classification the voltage across the sense resistor in the source of the MOSFET is measured and converted to a class level within the TPS2388. If a load short occurs during classification, the MOSFET gate voltage is quickly reduced to a linearly controlled, short-circuit value for the duration of the class event.

Classification results may be read through the I²C Detection Event and Port n Status Registers. The TPS2388 also supports two-event classification for type 2 PDs, using the IEEE Power Enable register.

8.4.4 DC Disconnect

Disconnect is the automated process of turning off power to the port. When the port is unloaded or at least falls below minimum load, it is necessary to turn off power to the port and restart detection. In DC disconnect, the voltage across the sense resistors is measured. When enabled, the DC disconnect function monitors the sense resistor voltage of a powered port to verify the port is drawing at least the minimum current to remain active. The TDIS timer counts up whenever the port current is below a 7.5-mA threshold. If a timeout occurs, the port is shut down and the corresponding disconnect bit in the Fault Event Register is set. The TDIS counter is reset each time the current goes continuously higher than the disconnect threshold for nominally 15 ms.

The TDIS duration is set by the TMPDO Bits of the Timing Configuration register (0x16).

8.5.1 I²C Serial Interface

The TPS2388 features a 3-wire I²C interface, using SDAI, SDAO, and SCL. Each transmission includes a Start condition sent by the master, followed by the device address (7-bit) with R/W bit, a register address byte, then one or two data bytes and a Stop condition. The recipient also sends an acknowledge bit following each byte transmitted. Also, SDAI/SDAO is stable while SCL is high except during a Start or Stop condition.

Figure 19 and Figure 20 illustrate read and write operations through I²C interface, using configuration A or B (see Table 19 for more details). The 'parametric' read operation is applicable to A/D conversion results. The TPS2388 also features quick access to the latest addressed register through I²C bus. This means that when a Stop bit is received, the register pointer is not automatically reset.

It is also possible to perform a write operation to many TPS2388 devices at the same time. The slave address during this broadcast access is 0x7F, as shown in Pin Status Register. Depending on which configuration (A or B) is selected, a global write proceeds as following:

• Config A: Both 4-port devices (1 to 4 and 5 to 8) are addressed at same time.
• Config B: The whole device is addressed.

Figure 19. I²C interface Read and Write Protocol – Configuration A

Figure 20. I²C interface Read and Write Protocol – Configuration B

8.6.1 Complete Register Set

8.6.2 INTERRUPT Register

COMMAND = 00h with 1 Data Byte, Read only

Active high, each bit corresponds to a particular event that occurred. Each bit can be individually reset by doing a read at the corresponding event register address, or by setting bit 7 of Reset register.

Any active bit of Interrupt register activates the INT output if its corresponding Mask bit in INTERRUPT Mask register (01h) is set, as well as the INTEN bit in the General Mask register.

8.6.3 INTERRUPT MASK Register

COMMAND = 01h with 1 Data Byte, Read/Write

Each bit corresponds to a particular event or fault as defined in the Interrupt register.

Writing a 0 into a bit will mask the corresponding event/fault from activating the INT output.

Note that the bits of the Interrupt register always change state according to events or faults, regardless of the state of the state of the Interrupt Mask register.

Note that the INTEN bit of the General Mask register must also be set in order to allow an event to activate the INT output.

SPACE

8.6.4 POWER EVENT Register

COMMAND = 02h with 1 Data Byte, Read only

COMMAND = 03h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual port.

A read at each location (02h or 03h) returns the same register data with the exception that the Clear on Read command clears all bits of the register.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

8.6.5 DETECTION EVENT Register

COMMAND = 04h with 1 Data Byte, Read only

COMMAND = 05h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual port.

A read at each location (04h or 05h) returns the same register data with the exception that the Clear on Read command clears all bits of the register. These bits are cleared when port n is turned off.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

8.6.6 FAULT EVENT Register

COMMAND = 06h with 1 Data Byte, Read only

COMMAND = 07h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual port.

A read at each location (06h or 07h) returns the same register data with the exception that the Clear on Read command clears all bits of the register. These bits are cleared when port n is turned off.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

Note that if ICUT is disabled for a port, this port will not be automatically turned off during an ICUT fault condition. However, the ICUT fault flag will still be operational, with a fault timeout equal to t_LIM / 2.

Also, if a Clear on Read is done at the Fault Event register, not only the ICUTn bit is reset, but the associated port ICUT counter is also reset.

Note that this has no impact on TLIM counter at all.

In any other case, ICUT fault is related to TOVLD fault timer as usual and there is no counter reset during clear on read operation.

8.6.7 START/ILIM EVENT Register

COMMAND = 08h with 1 Data Byte, Read only

COMMAND = 09h with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit xxx1-4 represents an individual port.

A read at each location (08h or 09h) returns the same register data with the exception that the Clear on Read command clears all bits of the register. These bits are cleared when port n is turned off.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

Note: When a Start Fault is reported after the IEEE Power Enable command is used, if the PECn bit in Power Event register is set, then there is an Inrush fault. If PECn bit is not set, then the Power-On Fault register indicates the cause of the fault.

8.6.8 SUPPLY EVENT Register

COMMAND = 0Ah with 1 Data Byte, Read only

COMMAND = 0Bh with 1 Data Byte, Clear on Read

Active high, each bit corresponds to a particular event that occurred.

Each bit D3, D2, D1, and D0 are reserved for future use.

A read at each location (0Ah or 0Bh) returns the same register data with the exception that the Clear on Read command clears all bits of the register.

If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.

Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.

8.6.9 PORT 1 STATUS Register

COMMAND = 0Ch with 1 Data Byte, Read Only

8.6.10 PORT 2 STATUS Register

COMMAND = 0Dh with 1 Data Byte, Read Only

8.6.11 PORT 3 STATUS Register

COMMAND = 0Eh with 1 Data Byte, Read Only

8.6.12 PORT 4 STATUS Register

COMMAND = 0Fh with 1 Data Byte, Read Only

Bit Descriptions: These bits represent the most recent classification and detection results for port n. These bits are cleared when port n is turned off.

8.6.13 POWER STATUS Register

COMMAND = 10h with 1 Data Byte, Read only

Each bit represents the actual power status of a port.

Each bit xx1-4 represents an individual port..

These bits are cleared when port n is turned off, including if the turn off is caused by a fault condition.

8.6.14 Pin Status Register

COMMAND = 11h with 1 Data Byte, Read Only

8.6.15 OPERATING MODE Register

COMMAND = 12h with 1 Data Byte, Read/Write

8.6.16 DISCONNECT ENABLE Register

COMMAND = 13h with 1 Data Byte, Read/Write

Bit Descriptions: Defines the disconnect detection mechanism for each port.

8.6.17 DETECT/CLASS ENABLE Register

COMMAND = 14h with 1 Data Byte, Read/Write

Bit Descriptions:

Detection and classification enable for each port.

When in Manual mode, setting a bit means that only one cycle (detection or classification) is performed for the corresponding port. The bit is automatically cleared by the time the cycle has been completed.

Note that similar result can be obtained by writing to the Detect/Class Restart register.

It is also cleared if a port turn off (Power Enable register) is issued.

When in semiauto mode, as long as the port is kept off, detection and classification are performed continuously, as long as the class and detect enable bits are kept set, but the class will be done only if the detection was valid. A Detect/Class Restart PB command can also be used to set the CLEn and DETEn bits, if in semiauto mode.

During t_OVLD, t_LIM or t_START cool down cycle, any Detect/Class Enable command for that port will be delayed until end of cool-down period. Note that at the end of cool down cycle, one or more detection/class cycles are automatically restarted as described previously, if the class and/or detect enable bits are set.

8.6.18 Port Power Priority/ICUT Disable Register Name

COMMAND = 15h with 1 Data Byte, R/W

8.6.19 TIMING CONFIGURATION Register

COMMAND = 16h with 1 Data Byte, Read/Write

Bit Descriptions: These bits define the timing configuration for all four ports.

Note: the PGn and PEn bits (Power Status register) are cleared when there is a TLIM, TOVLD, TMPDO, or TSTART fault condition.

8.6.20 GENERAL MASK Register

COMMAND = 17h with 1 Data Byte, Read/Write

8.6.21 DETECT/CLASS RESTART Register

COMMAND = 18h with 1 Data Byte, Write Only

Push button register.

Each bit corresponds to a particular cycle (detect or class restart) per port. Each cycle can be individually triggered by writing a 1 at that bit location, while writing a 0 does not change anything for that event.

In Manual mode, a single cycle (detect or class restart) will be triggered while in Semiauto mode, it sets the corresponding bit in the Detect/Class Enable register.

A Read operation will return 00h.

During t_OVLD, t_LIM or t_START cool down cycle, any Detect/Class Restart command for that port will be accepted but the corresponding action will be delayed until end of cool-down period.

8.6.22 POWER ENABLE Register

COMMAND = 19h with 1 Data Byte, Write Only

Push button register.

Used to force a port(s) turn on or turn off in any mode except OFF mode. If TPON bit in the PoE Plus register is low, or if the PSE controller is configured in Manual mode, writing a 1 at that PWONn bit location will immediately turn on the associated port, regardless of the classification and detection status and regardless of the IEEE802.3 TPON timing specification. This is also the case if TPON is set and DETn bit is 0, in semiauto mode.

If TPON bit in the PoE Plus register is set, and DETn bit (DETECT/CLASS ENABLE register) is set and while in semiauto mode, writing a 1 at a PWONn bit will turn on the associated port but only if the IEEE802.3 TPON timing specification can be met and if the detection is valid (and class is valid if enabled). TPON specification is the time from the completion of a valid detection cycle to port turn ON.

If TPON specification cannot be met, a new detection cycle is restarted, followed by a classification cycle if enabled, at the end of which the port is turned on, but only if a valid detection is returned and the IEEE802.3 TPON specification can be met. For this case, there is no additional attempt to turn on the port until this push button is reasserted. If the last detection result is not valid, the port is not turned on.

Note that in semiauto, as long as the port is kept off, detection and classification are performed continuously, if the corresponding class and detect enable bits are set.

Writing a 1 at POFFn location turns off the associated port.

Note that writing a 1 at POFFn and PWONn of same port during the same write operation turns the port off.

Also note that t_OVLD, t_LIM, t_START, and disconnect events have priority over the power on command. During t_OVLD, t_LIM, or t_START cool down cycle, any port turn on using Power Enable command will be ignored and the port will be kept off.

Turning OFF a port with this command also clears the corresponding bits in Detection Event register (CLSCn, DETCn), Fault Event register (DISFn, ICUTn), Start Event register (STRTn, ILIMn), Port n Status register (CLASS Pn, DETECT Pn), DETECT/CLASS ENABLE register (CLEn, DETEn) and Power-on Fault register (PFn). The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. The corresponding PEn and PGn bits of Power Status Register are also updated accordingly.

8.6.23 RESET Register

COMMAND = 1Ah with 1 Data Byte, Write Only

Push button register.

Writing a 1 at a bit location triggers an event while a 0 has no impact. Self-clearing bits.

8.6.24 ID Register

COMMAND = 1Bh with 1 Data Byte, Read/Write

8.6.25 Police 21 Configuration Register

COMMAND = 1Eh with 1 Data Byte, Read/Write

Replaces the ICUT mechanism. The threshold is defined with the Police bits and the PoE Plus register.

8.6.26 Police 43 Configuration Register

COMMAND = 1Fh with 1 Data Byte, Read/Write

Replaces the ICUT mechanism. The threshold is defined with the Police bits and the PoE Plus register.

8.6.27 IEEE Power Enable Register

COMMAND = 23h with 1 Data Byte, Write Only

Used to do a port(s) turn on during semiauto mode. This command is ignored if in manual mode. Note that if at completion of this command the addressed port is not turned on, the corresponding bits in the Detect/Class Enable register (register 14h) are being set, which means that detection and classification are performed continuously, as long as the class and detect enable bits are kept set.

Writing a 1 at a TmPONn bit will turn on the associated port but only if the IEEE802.3 TPON timing specification can be met. TPON specification is the time from the completion of a valid detection cycle to port turn ON.

If TPON specification cannot be met, a new detection cycle is restarted, followed by a classification cycle, at the end of which the port is turned on, but only if a valid detection and classification is returned. For this case, there is no additional attempt to turn on the port until this push button is reasserted.

Note that a port turn on will be performed only after both its current detection and classification cycle are completed

Note that writing a 1 at T1PONn and T2PONn of same port during the same write operation is interpreted as a T1PONn.

The corresponding PGCn and PECn bits of Power Event register will also be set depending on the result, while the CLSCn and DETCn bits of Detection Event register will be set based on the result and the CLCHE and DECHE bits in the General Mask register.

Also note that t_OVLD, t_LIM, t_START, and disconnect events are prioritary over the power on command. During t_OVLD, t_LIM, or t_START cool down cycle, any port turn on using IEEE Power Enable command will be ignored and the port will be kept off.

8.6.28 Power-on Fault Register

COMMAND = 24h with 1 Data Byte, Read Only

COMMAND = 25h with 1 Data Byte, Clear on Read

8.6.29 PORT RE-MAPPING Register

COMMAND = 26h with 1 Data Byte, Read/Write

8.6.30 Port 21 Multi Bit Priority Register

COMMAND = 27h with 1 Data Byte, Read/Write .

8.6.31 Port 43 Multi Bit Priority Register

COMMAND = 28h with 1 Data Byte, Read/Write

8.6.32 TEMPERATURE Register

COMMAND = 2Ch with 1 Data Byte, Read Only

8.6.33 INPUT VOLTAGE Register

COMMAND = 2Eh with 2 Data Byte (LSByte first, MSByte second), Read only

8.6.34 PORT 1 CURRENT Register

COMMAND = 30h with 2 Data Byte, (LSByte First, MSByte second), Read Only

8.6.35 PORT 2 CURRENT Register

COMMAND = 34h with 2 Data Byte, (LSByte First, MSByte second), Read Only

8.6.36 PORT 3 CURRENT Register

COMMAND = 38h with 2 Data Byte, (LSByte First, MSByte second), Read Only

8.6.37 PORT 4 CURRENT Register

COMMAND = 3Ch with 2 Data Byte, (LSByte First, MSByte second), Read Only

8.6.38 PORT 1 VOLTAGE Register

COMMAND = 32h with 2 Data Byte, (LSByte First, MSByte second), Read Only

8.6.39 PORT 2 VOLTAGE Register

COMMAND = 36h with 2 Data Byte, (LSByte First, MSByte second), Read Only

8.6.40 PORT 3 VOLTAGE Register

COMMAND = 3Ah with 2 Data Byte, (LSByte First, MSByte second), Read Only

8.6.41 PORT 4 VOLTAGE Register

COMMAND = 3Eh with 2 Data Byte, (LSByte First, MSByte second), Read Only

8.6.42 PoE Plus Register

COMMAND = 40h with1 Data Byte Read/Write

8.6.43 FIRMWARE REVISION

COMMAND = 41h with 1 Data Byte, Read Only

8.6.44 I2C WATCHDOG Register

COMMAND = 42h with 1 Data Byte, Read/Write

The I²C watchdog timer monitors the I²C clock line in order to prevent hung software situations that could leave ports in a hazardous state. The timer can be reset by either edge on SCL input. If the watchdog timer expires, all ports will be turned off and WDS bit will be set. The nominal watchdog time-out period is 2 seconds.

8.6.45 DEVICE ID Register

COMMAND = 43h with 1 Data Byte, Read Only

8.6.46 PORT 1 DETECT RESISTANCE Register

COMMAND = 44h with 1 Data Byte, Read Only

8.6.47 PORT 2 DETECT RESISTANCE Register

COMMAND = 45h with 1 Data Byte, Read Only

8.6.48 PORT 3 DETECT RESISTANCE Register

COMMAND = 46h with 1 Data Byte, Read Only

8.6.49 PORT 4 DETECT RESISTANCE Register

COMMAND = 47h with 1 Data Byte, Read Only