ZHCSGR0A February   2015  – August 2017 TPS2388

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1. 5.1 Detailed Pin Description
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Port Remapping
      2. 8.3.2 Port Power Priority
      3. 8.3.3 A/D Converter
      4. 8.3.4 I2C Watchdog
      5. 8.3.5 Foldback Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Port Operating Modes
        1. 8.4.1.1 Semiauto
        2. 8.4.1.2 Manual
        3. 8.4.1.3 Power Off
      2. 8.4.2 Detection
      3. 8.4.3 Classification
      4. 8.4.4 DC Disconnect
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1  Complete Register Set
      2. 8.6.2  INTERRUPT Register
      3. 8.6.3  INTERRUPT MASK Register
      4. 8.6.4  POWER EVENT Register
      5. 8.6.5  DETECTION EVENT Register
      6. 8.6.6  FAULT EVENT Register
      7. 8.6.7  START/ILIM EVENT Register
      8. 8.6.8  SUPPLY EVENT Register
      9. 8.6.9  PORT 1 STATUS Register
      10. 8.6.10 PORT 2 STATUS Register
      11. 8.6.11 PORT 3 STATUS Register
      12. 8.6.12 PORT 4 STATUS Register
      13. 8.6.13 POWER STATUS Register
      14. 8.6.14 Pin Status Register
      15. 8.6.15 OPERATING MODE Register
      16. 8.6.16 DISCONNECT ENABLE Register
      17. 8.6.17 DETECT/CLASS ENABLE Register
      18. 8.6.18 Port Power Priority/ICUT Disable Register Name
      19. 8.6.19 TIMING CONFIGURATION Register
      20. 8.6.20 GENERAL MASK Register
      21. 8.6.21 DETECT/CLASS RESTART Register
      22. 8.6.22 POWER ENABLE Register
      23. 8.6.23 RESET Register
      24. 8.6.24 ID Register
      25. 8.6.25 Police 21 Configuration Register
      26. 8.6.26 Police 43 Configuration Register
      27. 8.6.27 IEEE Power Enable Register
      28. 8.6.28 Power-on Fault Register
      29. 8.6.29 PORT RE-MAPPING Register
      30. 8.6.30 Port 21 Multi Bit Priority Register
      31. 8.6.31 Port 43 Multi Bit Priority Register
      32. 8.6.32 TEMPERATURE Register
      33. 8.6.33 INPUT VOLTAGE Register
      34. 8.6.34 PORT 1 CURRENT Register
      35. 8.6.35 PORT 2 CURRENT Register
      36. 8.6.36 PORT 3 CURRENT Register
      37. 8.6.37 PORT 4 CURRENT Register
      38. 8.6.38 PORT 1 VOLTAGE Register
      39. 8.6.39 PORT 2 VOLTAGE Register
      40. 8.6.40 PORT 3 VOLTAGE Register
      41. 8.6.41 PORT 4 VOLTAGE Register
      42. 8.6.42 PoE Plus Register
      43. 8.6.43 FIRMWARE REVISION
      44. 8.6.44 I2C WATCHDOG Register
      45. 8.6.45 DEVICE ID Register
      46. 8.6.46 PORT 1 DETECT RESISTANCE Register
      47. 8.6.47 PORT 2 DETECT RESISTANCE Register
      48. 8.6.48 PORT 3 DETECT RESISTANCE Register
      49. 8.6.49 PORT 4 DETECT RESISTANCE Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Introduction to PoE
      2. 9.1.2 TPS2388 Application
      3. 9.1.3 Kelvin Current Sensing Resistor
      4. 9.1.4 Connections on Unused Ports
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Pin Bypass Capacitors
        2. 9.2.2.2 Per Port Components
        3. 9.2.2.3 System Level Components (not shown in the schematic diagrams)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement and Routing Guidelines
        1. 11.2.1.1 Power Pin Bypass Capacitors
        2. 11.2.1.2 Per-Port Components
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Introduction to PoE

Power-over-Ethernet (PoE) is a means of distributing power to Ethernet devices over the Ethernet cable using either data or spare pairs. PoE eliminates the need for power supplies at the Ethernet device. Common applications of PoE are security cameras, IP Phones and PDA chargers. The host or mid-span equipment that supplies power is the power source equipment (PSE). The load at the Ethernet connector is the powered device (PD). PoE protocol between PSE and PD controlling power to the load is specified by IEEE Std 802.3at-2009. Transformers are used at Ethernet host ports, mid-spans and hubs, to interface data to the cable. A DC voltage can be applied to the center tap of the transformer with no effect on the data signals. As in any power transmission line, a relatively high 48 V is used to keep current low, minimize the effect of IR drops in the line and preserve power to the load. Standard POE delivers approximately 13 W to a type 1 PD, and 25.5 W to a type 2 PD.

9.1.2 TPS2388 Application

The TPS2388 is an 8-port, IEEE 802.3at PoE PSE controller and can be used in high port count semiauto or fully micro-controller managed applications (The MSP430G2553 micro-controller is recommended for most applications). Subsequent sections describe detailed design procedures for applications with different requirements including host control.

The schematic of Figure 71 depicts semiauto mode operation of the TPS2388, providing functionality to power PoE loads. In Figure 71 the TPS2388 can do the following:

  1. Performs load detection.
  2. Performs classification including type-2 (two-finger) of up to Class 4 loads.
  3. Enables power with protective foldback current limiting, and POLICE (ICUT) value.
  4. Shuts down in the event of fault loads and shorts.
  5. Performs Maintain Power Signature function to insure removal of power if load is disconnected.
  6. Undervoltage lock out occurs if VPWR falls below VPUV_F (typical 26.5 V).

Following a power-off command, disconnect or shutdown due to a start, ICUT or ILIM fault, the port powers down. Following port power off due to a power off command or disconnect, the TPS2388 will restart a detection cycle if commanded to do so through I2C bus. If the shutdown is due to a start, ICUT or ILIM fault, the TPS2388 enters into a cool-down period during which any Detect/Class Enable Command for that port will be delayed. At the end of cool down cycle, one or more detection/class cycles are automatically restarted if the class and/or detect enable bits are set.

9.1.3 Kelvin Current Sensing Resistor

Load current in each PSE port is sensed as the voltage across a low-end current-sense resistor with a value of 255 mΩ. For more accurate current sensing, kelvin sensing of the low end of the current-sense resistor is provided through pins KSENSA for ports 1 and 2, KSENSB for ports 3 and 4, KSENSC for ports 5 and 6 and KSENSD for ports 7 and 8.

TPS2388 K_Current_sense_conn_LUSC24.gif Figure 69. Kelvin Current-Sense Connection

9.1.4 Connections on Unused Ports

On unused ports, it is recommended to ground the SENx pin and leave the GATx pin open. DRAINx pins can be grounded or left open (leaving open may slightly reduce power consumption). Figure 70 shows an example of an unused PORT4.

TPS2388 Unused_Port4_conn_LUSC24.gif Figure 70. Unused PORT4 Connections

9.2 Typical Application

This typical application shows an eight port, semiauto mode application using MSP430 microcontroller. Operation in any mode requires I2C host support. The TPS2388 provides useful telemetry in multi-port applications to aid in implementing port power management.

TPS2388 8Port_semiauto_app_LUSC24.gif Figure 71. Eight Port Semiauto Mode Application

9.2.1 Design Requirements

The RESET pin may be connected to the micro-controller if an external RESET is required or connected directly to VDD. TPS2388 devices are used in the eight port configuration and are managed by the I2C host device. The I2C address for TPS2388 is programmed using the A4..A1 pins.

9.2.2 Detailed Design Procedure

9.2.2.1 Power Pin Bypass Capacitors

  • CVPWR: 0.1 μF, 100 V, X7R ceramic at pin 17 (VPWR)
  • CVDD: 0.1 μF, 50 V, X7R ceramic at pin 43 (VDD)

9.2.2.2 Per Port Components

  • CPn: 0.1-μF, 100-V, X7R ceramic between VPWR and Pn-
  • RSnA / RSnB: The port current sense resistors are a combination of two 0.51-Ω, 1% resistors in parallel (0.255 Ω). Dual 0.51-Ω, 1%, 0.25-W resistors in an 0805 SMT package are recommended. If a nominal 640 mA Policing (ICUT) threshold is selected, the maximum power dissipation for the resistor pair becomes approximately 115 mW (~57 mW each).
  • QPn: The port MOSFET can be a small, inexpensive device with average performance characteristics. BVDSS should be 100 V minimum. Target a MOSFET RDS(on) at VGS = 10 V of between 50 mΩ and 150 mΩ. The MOSFET GATE charge (QG) and input capacitance (CISS) should be less than 50 nC and 2000 pF respectively. The maximum power dissipation for QPn with RDS(on) = 100 mΩ at 640 mA nominal policing (ICUT) threshold is approximately 45 mW.
  • FPn: The port fuse should be a slow blow type rated for at least 60 VDC and above ~2 x ICUT(max). The cold resistance should be below 200 mΩ to reduce the DC losses. The power dissipation for FPn with a cold resistance of 180 mΩ at maximum ICUT is approximately 81 mW.
  • DPnA: The port TVS should be rated for the expected port surge environment. DPnA should have a minimum reverse standoff voltage of 58 V, peak pulse power rating of 600 W, and a maximum clamping voltage of less than 95 V at the expected peak surge current

9.2.2.3 System Level Components (not shown in the schematic diagrams)

The system TVS and bulk VPWR capacitance work together to protect the PSE system from surge events which could cause VPWR to surge above 70 V. The TVS and bulk capacitors should be placed on the PCB such that all TPS2388 ports are adequately protected.

  • TVS: The system TVS should have a minimum reverse standoff voltage of 58 V and a peak pulse power rating of 600 W or 1500 W depending on the total number of system ports and amount of bulk VPWR capacitance used. Together with the VPWR bulk capacitance, the TVS must prevent the VPWR rail from exceeding 70 V.
  • Bulk Capacitor: The system bulk capacitor(s) should be rated for 100 V and can be of aluminum electrolytic type. Two 47-μF capacitors can be used for each TPS2388 on board.
  • Distributed Capacitance:In higher port count systems, it may be necessary to distribute 1-uF, 100-V, X7R ceramic capacitors across the 48-V power bus. One capacitor per each TPS2388 pair is recommended.
  • Digital I/O Pullup Resistors: RESET and A1-A4 are internally pulled up to VDD, while OSS is internally pulled down, each with a 50-kΩ (typical) resistor. A stronger pull-up/down resistor can be added externally such as a 10 kΩ, 1%, 0.063 W type in a SMT package. SCL, SDAI, SDAO, and INT require external pull-up resistors within a range of 1 kΩ to 10 kΩ depending on the total number of devices on the bus .
  • Ethernet Data Transformer (per port): The Ethernet data transformer must be rated to operate within the IEEE802.3at standard in the presence of the DC port current conditions. The transformer is also chosen to be compatible with the Ethernet PHY. The transformer may also be integrated into the RJ45 connector and cable terminations.
  • RJ45 Connector (per port): The majority of the RJ45 connector requirements are mechanical in nature and include tab orientation, housing type (shielded or unshielded), or highly integrated. An integrated RJ45 consists of the Ethernet data transformer and cable terminations at a minimum. The integrated type may also contain the port TVS and common mode EMI filtering.
  • Cable Terminations (per port): The cable terminations typically consist of series resistor (usually 75 Ω) and capacitor (usually 10 nF) circuits from each data transformer center tap to a common node which is then bypassed to a chassis ground (or system earth ground) with a high-voltage capacitor (usually 1000 pF to 4700 pF at 2 kV).

9.2.3 Application Curves

TPS2388 typ_01_Startup_Valid_PD_CLASS_0_LUSC25.png
Figure 72. Startup With Valid PD (25 kΩ and 0.1 μF), Class 0
TPS2388 typ_03_Detection_Invalid_PD_LUSC25.png
Figure 74. Detection With Invalid PD (15 kΩ and 0.1 μF)
TPS2388 typ_05_Detection_Invalid_PD_25_kohm_LUSC25.png
Figure 76. Detection With Invalid PD (25 kΩ and 10 μF)
TPS2388 typ_07_Powering_Up_100_microF_Load_LUSC25.png
Figure 78. Powering Up into a 100-μF Load
TPS2388 typ_09_All_Ports_Fast_Shutdown_OSS_Input_LUSC25.png
Figure 80. All Ports Fast Shutdown from OSS Input
TPS2388 typ_11_Overcurrent_ICUT_Timeout_LUSC25.png
Figure 82. Overcurrent (ICUT) Timeout
TPS2388 typ_13_Rapid_Response_1_ohm_Short_PoE_LUSC25.png
Figure 84. Rapid Response to a 1-Ω Short - PoE+ Mode
TPS2388 typ_15_Response_25_ohm_Load_PoE_LUSC25.png
Figure 86. Response to a 25-Ω Load - PoE+ Mode
TPS2388 typ_17_Current_Limit_15_ms_Timeout_PoE_45_ohm_Load_LUSC25.png
Figure 88. Current Limit 15-ms Timeout - PoE+ Mode, 45-Ω Load
TPS2388 typ_19_Current_Limit_Timeout_Restart_Delay_LUSC25.png
Figure 90. Current Limit Timeout Restart Delay
TPS2388 app_01_LUSC24.gif Figure 92. Detection With Open Circuit
TPS2388 app_03_LUSC24.gif Figure 94. 2-Event Class and Port Turn On
TPS2388 typ_02_Startup_Valid_PD_CLASS_3_LUSC25.png
Figure 73. Startup With Valid PD (25 kΩ and 0.1 μF), Class 3
TPS2388 typ_04_Detection_Invalid_PD_open_cir_LUSC25.png
Figure 75. Detection With Invalid PD (Open Circuit)
TPS2388 typ_06_2_Event_Class_Startup_Valid_PD_LUSC25.png
Figure 77. 2-Event Class and Startup With Valid PD
TPS2388 typ_08_All_Ports_Power_On_TPON_Bit_Set_LUSC25.png
Figure 79. All Ports Power-On With TPON Bit Set
TPS2388 typ_10_Ports_Fast_Shutdown_3_bit_OSS_Input_LUSC25.png
Figure 81. Ports Fast Shutdown from 3-Bit OSS Input
TPS2388 typ_12_Rapid_Response_1_ohm_Short_802.3af_LUSC25.png
Figure 83. Rapid Response to a 1-Ω Short - 802.3af Mode
TPS2388 typ_14_Response_50_ohm_Load_802.3af_LUSC25.png
Figure 85. Response to a 50-Ω Load - 802.3af Mode
TPS2388 typ_16_Current_Limit_Timeout_802.3af_85_ohm_LUSC25.png
Figure 87. Current Limit Timeout - 802.3af Mode, 85-Ω Load
TPS2388 typ_18_Inrush_Fault_Timeout_100_ohm_Load_LUSC25.png
Figure 89. Inrush Fault Timeout - 100-Ω Load
TPS2388 typ_20_Response_to_8_to_6_mA_Load_DC_Disconnect_LUSC25.png
Figure 91. Response to 8-mA to 6-mA Load, DC Disconnect Enabled
TPS2388 app_02_LUSC24.gif Figure 93. Detection, 2-Event Class and Port Turn On
TPS2388 app_04_LUSC24.gif Figure 95. 2-Event Class and Port Turn On