ZHCSGR0A February   2015  – August 2017 TPS2388

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1. 5.1 Detailed Pin Description
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Timing Diagrams
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Port Remapping
      2. 8.3.2 Port Power Priority
      3. 8.3.3 A/D Converter
      4. 8.3.4 I2C Watchdog
      5. 8.3.5 Foldback Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Port Operating Modes
        1. 8.4.1.1 Semiauto
        2. 8.4.1.2 Manual
        3. 8.4.1.3 Power Off
      2. 8.4.2 Detection
      3. 8.4.3 Classification
      4. 8.4.4 DC Disconnect
    5. 8.5 Programming
      1. 8.5.1 I2C Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1  Complete Register Set
      2. 8.6.2  INTERRUPT Register
      3. 8.6.3  INTERRUPT MASK Register
      4. 8.6.4  POWER EVENT Register
      5. 8.6.5  DETECTION EVENT Register
      6. 8.6.6  FAULT EVENT Register
      7. 8.6.7  START/ILIM EVENT Register
      8. 8.6.8  SUPPLY EVENT Register
      9. 8.6.9  PORT 1 STATUS Register
      10. 8.6.10 PORT 2 STATUS Register
      11. 8.6.11 PORT 3 STATUS Register
      12. 8.6.12 PORT 4 STATUS Register
      13. 8.6.13 POWER STATUS Register
      14. 8.6.14 Pin Status Register
      15. 8.6.15 OPERATING MODE Register
      16. 8.6.16 DISCONNECT ENABLE Register
      17. 8.6.17 DETECT/CLASS ENABLE Register
      18. 8.6.18 Port Power Priority/ICUT Disable Register Name
      19. 8.6.19 TIMING CONFIGURATION Register
      20. 8.6.20 GENERAL MASK Register
      21. 8.6.21 DETECT/CLASS RESTART Register
      22. 8.6.22 POWER ENABLE Register
      23. 8.6.23 RESET Register
      24. 8.6.24 ID Register
      25. 8.6.25 Police 21 Configuration Register
      26. 8.6.26 Police 43 Configuration Register
      27. 8.6.27 IEEE Power Enable Register
      28. 8.6.28 Power-on Fault Register
      29. 8.6.29 PORT RE-MAPPING Register
      30. 8.6.30 Port 21 Multi Bit Priority Register
      31. 8.6.31 Port 43 Multi Bit Priority Register
      32. 8.6.32 TEMPERATURE Register
      33. 8.6.33 INPUT VOLTAGE Register
      34. 8.6.34 PORT 1 CURRENT Register
      35. 8.6.35 PORT 2 CURRENT Register
      36. 8.6.36 PORT 3 CURRENT Register
      37. 8.6.37 PORT 4 CURRENT Register
      38. 8.6.38 PORT 1 VOLTAGE Register
      39. 8.6.39 PORT 2 VOLTAGE Register
      40. 8.6.40 PORT 3 VOLTAGE Register
      41. 8.6.41 PORT 4 VOLTAGE Register
      42. 8.6.42 PoE Plus Register
      43. 8.6.43 FIRMWARE REVISION
      44. 8.6.44 I2C WATCHDOG Register
      45. 8.6.45 DEVICE ID Register
      46. 8.6.46 PORT 1 DETECT RESISTANCE Register
      47. 8.6.47 PORT 2 DETECT RESISTANCE Register
      48. 8.6.48 PORT 3 DETECT RESISTANCE Register
      49. 8.6.49 PORT 4 DETECT RESISTANCE Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Introduction to PoE
      2. 9.1.2 TPS2388 Application
      3. 9.1.3 Kelvin Current Sensing Resistor
      4. 9.1.4 Connections on Unused Ports
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Pin Bypass Capacitors
        2. 9.2.2.2 Per Port Components
        3. 9.2.2.3 System Level Components (not shown in the schematic diagrams)
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 VDD
    2. 10.2 VPWR
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Port Current Kelvin Sensing
    2. 11.2 Layout Example
      1. 11.2.1 Component Placement and Routing Guidelines
        1. 11.2.1.1 Power Pin Bypass Capacitors
        2. 11.2.1.2 Per-Port Components
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Layout

11.1 Layout Guidelines

11.1.1 Port Current Kelvin Sensing

KSENSA is shared between SEN1 and SEN2, KSENSB is shared between SEN3 and SEN4, KSENSC is shared between SEN5 and SEN6, and KSENSD is shared between SEN7 and SEN8. To optimize the accuracy of the measurement, the PCB layout must be done carefully to minimize impact of PCB trace resistance. Refer to as an example.

TPS2388 K_sense_Layout_ex_LUSC25.png Figure 96. Kelvin Sense Layout Example

11.2 Layout Example

TPS2388 8port_layout_ex_LUSC24.gif Figure 97. Eight Port Layout Example (Top Side)

11.2.1 Component Placement and Routing Guidelines

11.2.1.1 Power Pin Bypass Capacitors

  • CVPWR: Place close to pin 17 (VPWR) and connect with low inductance traces and vias according to Figure 97.
  • CVDD: Place close to pin 43 (VDD) and connect with low inductance traces and vias according to Figure 97

11.2.1.2 Per-Port Components

  • RSnA / RSnB: Place according to in a manner that facilitates a clean Kelvin connection with KSENSEA/B/C/D.
  • QPn: Place QPn around the TPS2388 as illustrated in Figure 97. Provide sufficient copper from QPn drain to FPn.
  • FPn, CPn, DPnA, DPnB: Place this circuit group near the RJ45 port connector (or port power interface if a daughter board type of interface is used as illustrated in Figure 97). Connect this circuit group to QPn drain or GND (TPS2388- AGND) using low inductance traces.