ZHCSDK9A March   2015  – April 2015 TPS22953 , TPS22954

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Electrical Characteristics, VBIAS = 5 V
    7. 8.7  Electrical Characteristics, VBIAS = 3.3 V
    8. 8.8  Electrical Characteristics, VBIAS = 2.5 V
    9. 8.9  Switching Characteristics, CT = 1000 pF
    10. 8.10 Switching Characteristics, CT = 0 pF
    11. 8.11 Typical DC Characteristics
    12. 8.12 Typical Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 On/Off Control (EN pin)
      2. 9.3.2 Voltage Monitoring (SNS pin)
      3. 9.3.3 Power Good (PG Pin)
      4. 9.3.4 Supervisor Fault Detection and Automatic Restart
      5. 9.3.5 Manual Restart
      6. 9.3.6 Thermal Shutdown
      7. 9.3.7 Quick Output Discharge (QOD) (TPS22954 Only)
      8. 9.3.8 VIN and VBIAS Voltage Range
      9. 9.3.9 Adjustable Rise Time (CT pin)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input to OutputVoltage Drop
      2. 10.1.2 Thermal Considerations
      3. 10.1.3 Automatic Power Sequencing
      4. 10.1.4 Monitoring a Downstream Voltage
        1. 10.1.4.1 Monitoring the Input Voltage
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 相关链接
    2. 13.2 商标
    3. 13.3 静电放电警告
    4. 13.4 术语表
  14. 14机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

12 Layout

12.1 Layout Guidelines

  • Input and Output traces should be as short and wide as possible to accommodate for high current.
  • Use vias under the exposed thermal pad for thermal relief for high current operation.
  • The CT Capacitor should be placed as close as possible to the device to minimize parasitic trace capacitance. It is also recommended to cutout copper on other layers directly below CT to minimize parasitic capacitance.
  • The IN terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device pins as possible.
  • The OUT terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is ceramic with X5R or X7R dielectric. This capacitor should be placed as close to the device pins as possible.
  • The BIAS terminal should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is ceramic with X5R or X7R dielectric.

12.2 Layout Example

TPS22954 TPS22953 layout.gifFigure 64. Recommended Board Layout