ZHCS294F June   2011  – February 2024 TPA6211A1-Q1

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configuration and Functions
    1.     Pin Functions
    2. 4.1 DAPPER
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Operating Characteristics
    7. 5.7 Dissipation Ratings
    8.     Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Advantages of Fully Differential Amplifiers
      2. 6.3.2 Fully Differential Amplifier Efficiency and Thermal Information
      3. 6.3.3 Differential Output Versus Single-Ended Output
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Typical Differential Input Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Resistors (RI)
          2. 7.2.1.2.2 Bypass Capacitor (CBYPASS) and Start-Up Time
          3. 7.2.1.2.3 Input Capacitor (CI)
          4. 7.2.1.2.4 Band-Pass Filter (RI, CI, and CF)
            1. 7.2.1.2.4.1 Step 1: Low-Pass Filter
            2. 7.2.1.2.4.2 Step 2: High-Pass Filter
            3. 7.2.1.2.4.3 Step 3: Additional Low-Pass Filter
          5. 7.2.1.2.5 Decoupling Capacitor (CS)
          6. 7.2.1.2.6 Using Low-ESR Capacitors
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Other Application Circuits
  9. Power Supply Recommendations
    1. 8.1 Power Supply Decoupling Capacitor
  10. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Community Resources
    3. 10.3 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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Electrical Characteristics

TA = 25°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VOSOutput offset voltage (measured differentially)VI = 0-V differential, Gain = 1 V/V, VDD = 5.5 V–90.39mV
PSRRPower supply rejection ratioVDD = 2.5 V to 5.5 V–85–60dB
VICCommon mode input rangeVDD = 2.5 V to 5.5 V0.5VDD – 0.8V
CMRRCommon mode rejection ratioVDD = 5.5 V, VIC = 0.5 V to 4.7 V–63–40dB
VDD = 2.5 V, VIC = 0.5 V to 1.7 V–63–40
Low-output swingRL = 4 Ω, VIN+ = VDD, VIN+ = 0 V,
Gain = 1 V/V, VIN– = 0 V or VIN– = VDD
VDD = 5.5 V0.45V
VDD = 3.6 V0.37
VDD = 2.5 V0.260.4
High-output swingRL = 4 Ω, VIN+ = VDD, VIN– = VDD,
Gain = 1 V/V, VIN– = 0 V or VIN+ = 0 V
VDD = 5.5 V4.95V
VDD = 3.6 V3.18
VDD = 2.5 V22.13
| IIH |High-level input current, shutdownVDD = 5.5 V, VI = 5.8 V58100µA
| IIL |Low-level input current, shutdownVDD = 5.5 V, VI = –0.3 V3100µA
IQQuiescent currentVDD = 2.5 V to 5.5 V, no load45mA
I(SD)Supply currentVSHUTDOWN ≤ 0.5 V, VDD = 2.5 V to 5.5 V, RL = 4 Ω0.011µA
GainRL = 4 ΩGUID-B72E1FA0-0CB3-4A8A-9B5D-8C4AA5E7AC65-low.gifGUID-CE3F7E97-D1EC-4B15-88F4-506E405BC045-low.gifGUID-32FE06C3-6E8F-49BB-B596-A25698359505-low.gifV/V
Resistance from shutdown to GND100kΩ