13.1 Layout Guidelines

In order for the PCB design to be successful, start with design of the protection and filtering circuitry. Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must be applied during PCB design. On-chip IEC ESD protection is good for laboratory and portable equipment but is usually not sufficient for EFT and surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires the use of external transient protection devices at the bus connectors. Placement at the connector also prevents these harsh transient events from propagating further into the PCB and system.

Use V_CC and ground planes to provide low inductance.

Design bus protection by placing the protective components in the signal path. Do not force the transient current to divert from the signal path to reach the protection device.

An example placement of the transient-voltage-suppression (TVS) device indicated as D1 (either bidirectional diode or varistor solution) and bus filter capacitors C8 and C9 is shown in Figure 42.

The bus transient protection and filtering components should be placed as close to the bus connector, J1, as possible. This prevents transients, ESD and noise from penetrating onto the board and disturbing other devices.

Bus termination: Figure 42 shows split termination. This is where the termination is split into two resistors, R5 and R6, with the center or split tap of the termination connected to ground via capacitor C7. Split termination provides common-mode filtering for the bus. When termination is placed on the board instead of directly on the bus, care must be taken to ensure the terminating node is not removed from the bus, as there are signal integrity issues if the bus is not properly terminated on both ends. See the Detailed Design Procedure section for information on power ratings needed for the termination resistor(s).

Bypass and bulk capacitors should be placed as close as possible to the supply pins of the transceiver, as in the example of C2 and C3 on V_CC.

Use at least two vias for the V_CC and ground connections of the bypass capacitors and protection devices to minimize trace and via inductance.

To limit current on the digital lines, serial resistors may be used. Examples are R1, R2, R3 and R4.

To filter noise on the digital I/O lines, a capacitor may be used close to the input side of the I/O as shown by C1 and C4.

Because the internal pullup and pulldown biasing of the device is weak for floating pins, an external 1-kΩ to 10‑kΩ pullup or pulldown resistor should be used to bias the state of the pin more strongly against noise during transient events.

Pin 1: If an open-drain host processor is used to drive the TXD pin of the device, an external pullup resistor between 1 kΩ and 10 kΩ to V_CC should be used to drive the recessive input state of the device.

Pin 8: The mode pin, RS, is shown, assuming that it is used in the application. If the device is only to be used in normal mode or slope-control mode, R3 is not needed and the pads of C4 could be used for the pulldown resistor to GND.

13.2 Layout Example

Figure 42. Layout Example Diagram