ZHCSPD7A April 2022 – September 2022 PCMD3140-Q1
PRODUCTION DATA
The PCMD3140-Q1 achieves low-noise performance by internally generating a low-noise reference voltage. This reference voltage is generated using a band-gap circuit with high PSRR performance and must be filtered externally using a 1-µF capacitor connected from the VREF pin to analog ground (AVSS).
The value of this reference voltage can be configured using the P0_R59_D[1:0] register bits and must be set to an appropriate value based on the AVDD supply voltage available in the system. The default VREF value is set to 2.75 V, which require minimum AVDD voltage for this mode is 3 V. Table 7-8 lists the various VREF settings supported along with required AVDD range for that configuration.
P0_R59_D[1:0] : VREF_SEL[1:0] | VREF OUTPUT VOLTAGE | AVDD RANGE REQUIREMENT |
---|---|---|
00 (default) | 2.75 V | 3 V to 3.6 V |
01 | 2.5 V | 2.8 V to 3.6 V |
10 | 1.375 V | 1.7 V to 1.9 V |
11 | Reserved | Reserved |
To achieve low-power consumption, this audio reference block is powered down as described in the Section 7.4.1 section. When exiting sleep mode, the audio reference block is powered up using the internal fast-charge scheme and the VREF pin settles to its steady-state voltage after the settling time (a function of the decoupling capacitor on the VREF pin). This time is approximately equal to 3.5 ms when using a 1-μF decoupling capacitor. If a higher-value decoupling capacitor is used on the VREF pin, the fast-charge setting must be reconfigured using the VREF_QCHG (P0_R2_D[4:3]) register bits, which support options of 3.5 ms (default), 10 ms, 50 ms, or 100 ms.