ZHCSPD7A April   2022  – September 2022 PCMD3140-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 6.9  Switching Characteristics: TDM, I2S or LJ Interface
    10.     Timing Requirements: PDM Digital Microphone Interface
    11. 6.10 Switching Characteristics: PDM Digial Microphone Interface
    12. 6.11 Timing Diagrams
    13. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3 Reference Voltage
      4. 7.3.4 Microphone Bias
      5. 7.3.5 Digital PDM Microphone Record Channel
      6. 7.3.6 Signal-Chain Processing
        1. 7.3.6.1 Programmable Digital Volume Control
        2. 7.3.6.2 Programmable Channel Gain Calibration
        3. 7.3.6.3 Programmable Channel Phase Calibration
        4. 7.3.6.4 Programmable Digital High-Pass Filter
        5. 7.3.6.5 Programmable Digital Biquad Filters
        6. 7.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 7.3.6.7 Configurable Digital Decimation Filters
          1. 7.3.6.7.1 Linear Phase Filters
            1. 7.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 7.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 7.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 7.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 7.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 7.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 7.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 7.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 7.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 7.3.6.7.2 Low-Latency Filters
            1. 7.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 7.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 7.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 7.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 7.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 7.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 7.3.6.7.3 Ultra-Low-Latency Filters
            1. 7.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 7.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 7.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 7.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 7.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 7.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 7.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 7.3.7 Voice Activity Detection (VAD)
      8. 7.3.8 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode or Software Shutdown
      2. 7.4.2 Active Mode
      3. 7.4.3 Software Reset
    5. 7.5 Programming
      1. 7.5.1 Control Serial Interfaces
        1. 7.5.1.1 I2C Control Interface
          1. 7.5.1.1.1 General I2C Operation
          2. 7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 7.5.1.1.2.1 I2C Single-Byte Write
            2. 7.5.1.1.2.2 I2C Multiple-Byte Write
            3. 7.5.1.1.2.3 I2C Single-Byte Read
            4. 7.5.1.1.2.4 I2C Multiple-Byte Read
    6. 7.6 Register Maps
      1. 7.6.1 Page 0 Registers
      2. 7.6.2 Page 1 Registers
      3. 7.6.3 Programmable Coefficient Registers
        1. 7.6.3.1 Programmable Coefficient Registers: Page 2
        2. 7.6.3.2 Programmable Coefficient Registers: Page 3
        3. 7.6.3.3 Programmable Coefficient Registers: Page 4
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Four-Channel Digital PDM Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 8.2.1.3 Application Curves
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.6.5 Programmable Digital Biquad Filters

The device supports up to 12 programmable digital biquad filters. These highly efficient filters achieve the desired frequency response. In digital signal processing, a digital biquad filter is a second-order, recursive linear filter with two poles and two zeros. Equation 2 gives the transfer function of each biquad filter:

Equation 2. GUID-BC2B8BC9-15A8-4F51-BCDC-655425304DBE-low.gif

The frequency response for the biquad filter section with default coefficients is flat at a gain of 0 dB (all-pass filter). The host device can override the frequency response by programming the biquad coefficients to achieve the desired frequency response for a low-pass, high-pass, or any other desired frequency shaping. The programmable coefficients for the mixer operation are located in the Section 7.6.3.1 and Section 7.6.3.2 sections. If biquad filtering is required, then the host device must write these coefficients values before powering up any PDM channels for recording. These programmable coefficients are 32-bit, two’s complement numbers. As described in Table 7-15, these biquad filters can be allocated for each output channel based on the BIQUAD_CFG[1:0] register setting of P0_R108. By setting BIQUAD_CFG[1:0] to 2'b00, the biquad filtering for all record channels is disabled and the host device can choose this setting if no additional filtering is required for the system application. See the TLV320ADCx140 Programmable Biquad Filter Configuration and Applications application report for further details.

Table 7-15 Biquad Filter Allocation to the Record Output Channel
PROGRAMMABLE BIQUAD FILTER RECORD OUTPUT CHANNEL ALLOCATION USING P0_R108_D[6:5] REGISTER SETTING
BIQUAD_CFG[1:0] = 2'b01
(1 Biquad per Channel)		 BIQUAD_CFG[1:0] = 2'b10 (Default)
(2 Biquads per Channel)		 BIQUAD_CFG[1:0] = 2'b11
(3 Biquads per Channel)
SUPPORTS ALL 8 CHANNELS SUPPORTS UP TO 6 CHANNELS SUPPORTS UP TO 4 CHANNELS
Biquad filter 1 Allocated to output channel 1 Allocated to output channel 1 Allocated to output channel 1
Biquad filter 2 Allocated to output channel 2 Allocated to output channel 2 Allocated to output channel 2
Biquad filter 3 Allocated to output channel 3 Allocated to output channel 3 Allocated to output channel 3
Biquad filter 4 Allocated to output channel 4 Allocated to output channel 4 Allocated to output channel 4
Biquad filter 5 Not used Allocated to output channel 1 Allocated to output channel 1
Biquad filter 6 Not used Allocated to output channel 2 Allocated to output channel 2
Biquad filter 7 Not used Allocated to output channel 3 Allocated to output channel 3
Biquad filter 8 Not used Allocated to output channel 4 Allocated to output channel 4
Biquad filter 9 Not used Not used Allocated to output channel 1
Biquad filter 10 Not used Not used Allocated to output channel 2
Biquad filter 11 Not used Not used Allocated to output channel 3
Biquad filter 12 Not used Not used Allocated to output channel 4

Table 7-16 shows the biquad filter coefficients mapping to the register space.

Table 7-16 Biquad Filter Coefficients Register Mapping
PROGRAMMABLE BIQUAD FILTER BIQUAD FILTER COEFFICIENTS REGISTER MAPPING PROGRAMMABLE BIQUAD FILTER BIQUAD FILTER COEFFICIENTS REGISTER MAPPING
Biquad filter 1 P2_R8-R27 Biquad filter 7 P3_R8-R27
Biquad filter 2 P2_R28-R47 Biquad filter 8 P3_R28-R47
Biquad filter 3 P2_R48-R67 Biquad filter 9 P3_R48-R67
Biquad filter 4 P2_R68-R87 Biquad filter 10 P3_R68-R87
Biquad filter 5 P2_R88-R107 Biquad filter 11 P3_R88-R107
Biquad filter 6 P2_R108-R127 Biquad filter 12 P3_R108-R127