ZHCSER2D May   2013  – October 2020 MSP430F5252 , MSP430F5253 , MSP430F5254 , MSP430F5255 , MSP430F5256 , MSP430F5257 , MSP430F5258 , MSP430F5259

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)
    8. 8.8  Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)
    9. 8.9  Inputs – Interrupts DVCC Domain Port P6 (P6.0 to P6.7)
    10. 8.10 Inputs – Interrupts DVIO Domain Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    11. 8.11 Leakage Current – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    12. 8.12 Leakage Current – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    13. 8.13 Outputs – General-Purpose I/O DVCC Domain (Full Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    14. 8.14 Outputs – General-Purpose I/O DVCC Domain (Reduced Drive Strength) (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    15. 8.15 Outputs – General-Purpose I/O DVIO Domain (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    16. 8.16 Outputs – General-Purpose I/O DVIO Domain (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    17. 8.17 Output Frequency – General-Purpose I/O DVCC Domain (P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3)
    18. 8.18 Output Frequency – General-Purpose I/O DVIO Domain (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5)
    19. 8.19 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    20. 8.20 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    21. 8.21 Crystal Oscillator, XT1, Low-Frequency Mode
    22. 8.22 Crystal Oscillator, XT2
    23. 8.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    24. 8.24 Internal Reference, Low-Frequency Oscillator (REFO)
    25. 8.25 DCO Frequency
    26. 8.26 PMM, Brownout Reset (BOR)
    27. 8.27 PMM, Core Voltage
    28. 8.28 PMM, SVS High Side
    29. 8.29 PMM, SVM High Side
    30. 8.30 PMM, SVS Low Side
    31. 8.31 PMM, SVM Low Side
    32. 8.32 Wake-up Times From Low-Power Modes and Reset
    33. 8.33 Timer_A
    34. 8.34 Timer_B
    35. 8.35 USCI (UART Mode) Clock Frequency
    36. 8.36 USCI (UART Mode)
    37. 8.37 USCI (SPI Master Mode) Clock Frequency
    38. 8.38 USCI (SPI Master Mode)
    39. 8.39 USCI (SPI Slave Mode)
    40. 8.40 USCI (I2C Mode)
    41. 8.41 10-Bit ADC, Power Supply and Input Range Conditions
    42. 8.42 10-Bit ADC, Timing Parameters
    43. 8.43 10-Bit ADC, Linearity Parameters
    44. 8.44 REF, External Reference
    45. 8.45 REF, Built-In Reference
    46. 8.46 Comparator_B
    47. 8.47 Flash Memory
    48. 8.48 JTAG and Spy-Bi-Wire Interface
    49. 8.49 DVIO BSL Entry
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
      1. 9.5.1 Bootloader – I2C
      2. 9.5.2 Bootloader – UART
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Port Mapping Controller
      3. 9.9.3  Oscillator and System Clock
      4. 9.9.4  Power-Management Module (PMM)
      5. 9.9.5  Hardware Multiplier
      6. 9.9.6  Real-Time Clock (RTC_A)
      7. 9.9.7  Watchdog Timer (WDT_A)
      8. 9.9.8  System Module (SYS)
      9. 9.9.9  DMA Controller
      10. 9.9.10 Universal Serial Communication Interface (USCI)
      11. 9.9.11 TA0
      12. 9.9.12 TA1
      13. 9.9.13 TA2
      14. 9.9.14 TB0
      15. 9.9.15 Comparator_B
      16. 9.9.16 ADC10_A
      17. 9.9.17 CRC16
      18. 9.9.18 Reference (REF) Module Voltage Reference
      19. 9.9.19 Embedded Emulation Module (EEM) (S Version)
      20. 9.9.20 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.4) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P7 (P7.0 to P7.5) Input/Output With Schmitt Trigger
      10. 9.10.10 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      11. 9.10.11 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  支持资源
    7. 10.7  Trademarks
    8. 10.8  静电放电警告
    9. 10.9  Export Control Notice
    10. 10.10 术语表
  11. 11Mechanical, Packaging, and Orderable Information

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订购信息

7.2 Signal Descriptions

Table 7-1 describes the device signals.

Table 7-1 Terminal Functions
TERMINAL I/O(1) SUPPLY DESCRIPTION
NAME NO.(2)
RGC ZXH, ZQE
P6.0/TA2CLK/SMCLK/CB0/A0 1 A1 I/O DVCC General-purpose digital I/O with port interrupt
TA2 clock signal TA2CLK input
SMCLK output
Comparator_B input CB0
Analog input A0 for ADC (not available on all device types)
P6.1/TA2.0/CB1/A1 2 B2 I/O DVCC General-purpose digital I/O with port interrupt
TA2 CCR0 capture: CCI0A input, compare: Out0 output
Comparator_B input CB1
Analog input A1 for ADC (not available on all device types)
BSL transmit output
P6.2/TA2.1/CB2/A2 3 B1 I/O DVCC General-purpose digital I/O with port interrupt
TA2 CCR1 capture: CCI1A input, compare: Out1 output
Comparator_B input CB2
Analog input A2 for ADC (not available on all device types)
BSL receive input
P6.3/TA2.2/CB3/A3 4 C2 I/O DVCC General-purpose digital I/O with port interrupt
TA2 CCR2 capture: CCI2A input, compare: Out2 output
Comparator_B input CB3
Analog input A3 for ADC (not available on all device types)
P6.4/CB4/A4 5 C1 I/O DVCC General-purpose digital I/O with port interrupt
Comparator_B input CB4
Analog input A4 for ADC (not available on all device types)
P6.5/CB5/A5 6 D2 I/O DVCC General-purpose digital I/O with port interrupt
Comparator_B input CB5
Analog input A5 for ADC (not available on all device types)
P6.6/CB6/A6 7 D1 I/O DVCC General-purpose digital I/O with port interrupt
Comparator_B input CB6
Analog input A6 for ADC (not available on all device types)
P6.7/CB7/A7 8 D3 I/O DVCC General-purpose digital I/O with port interrupt
Comparator_B input CB7
Analog input A7 for ADC (not available on all device types)
P5.0/A8/VeREF+ 9 E1 I/O DVCC General-purpose digital I/O
Analog input A8 for ADC (not available on all device types)
Input for an external reference voltage to the ADC (not available on all device types)
P5.1/A9/VeREF- 10 E2 I/O DVCC General-purpose digital I/O
Analog input A9 for ADC (not available on all device types)
Negative terminal for the ADC reference voltage for an external applied reference voltage (not available on all device types)
AVCC 11 F2 Analog power supply
P5.4/XIN 12 F1 I/O DVCC General-purpose digital I/O
Input terminal for crystal oscillator XT1(3)
P5.5/XOUT 13 G1 I/O DVCC General-purpose digital I/O
Output terminal of crystal oscillator XT1
AVSS 14 G2 Analog ground supply
DVCC 15 H1 Digital power supply
DVSS 16 J1 Digital ground supply
VCORE(4) 17 J2 DVCC Regulated core power supply output (internal use only, no external current loading)
P1.0/TA0CLK/ACLK(5) 18 H2 I/O DVIO General-purpose digital I/O with port interrupt
TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0(5) 19 H3 I/O DVIO General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
P1.2/TA0.1(5) 20 J3 I/O DVIO General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
P1.3/TA0.2(5) 21 G4 I/O DVIO General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3(5) 22 H4 I/O DVIO General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4(5) 23 J4 I/O DVIO General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA1CLK/CBOUT(5) 24 G5 I/O DVIO General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
Comparator_B output
P1.7/TA1.0(5) 25 H5 I/O DVIO General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.0/TA1.1(5) 26 J5 I/O DVIO General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
P2.1/TA1.2(5) 27 G6 I/O DVIO General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
P2.2/UCB3SIMO/UCB3SDA(5) 28 J6 I/O DVIO General-purpose digital I/O with port interrupt
Slave in, master out – USCI_B3 SPI mode
I2C data – USCI_B3 I2C mode
P2.3/UCB3SOMI/UCB3SCL(5) 29 H6 I/O DVIO General-purpose digital I/O with port interrupt
Slave out, master in – USCI_B3 SPI mode
I2C clock – USCI_B3 I2C mode
P2.4/UCB3CLK/UCA3STE(5) 30 J7 I/O DVIO General-purpose digital I/O with port interrupt
Clock signal input – USCI_B3 SPI slave mode
Clock signal output – USCI_B3 SPI master mode
Slave transmit enable – USCI_A3 SPI mode
P2.5/UCB3STE/UCA3CLK(5) 31 J8 I/O DVIO General-purpose digital I/O with port interrupt
Slave transmit enable – USCI_B3 SPI mode
Clock signal input – USCI_A3 SPI slave mode
Clock signal output – USCI_A3 SPI master mode
P2.6/RTCCLK/DMAE0(5) 32 J9 I/O DVIO General-purpose digital I/O with port interrupt
RTC clock output for calibration
DMA external trigger input
P2.7/UCB0STE/UCA0CLK(5) 33 H7 I/O DVIO General-purpose digital I/O
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
P3.0/UCB0SIMO/UCB0SDA(5) 34 H8 I/O DVIO General-purpose digital I/O
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
P3.1/UCB0SOMI/UCB0SCL(5) 35 H9 I/O DVIO General-purpose digital I/O
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
P3.2/UCB0CLK/UCA0STE(5) 36 G8 I/O DVIO General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
P3.3/UCA0TXD/UCA0SIMO(5) 37 G9 I/O DVIO General-purpose digital I/O
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
P3.4/UCA0RXD/UCA0SOMI(5) 38 G7 I/O DVIO General-purpose digital I/O
Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
DVSS 39 F9 Digital ground supply
DVIO(6) 40 E9 Digital I/O power supply
P4.0/PM_UCB1STE/ PM_UCA1CLK(5) 41 E8 I/O DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave transmit enable – USCI_B1 SPI mode
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode
P4.1/PM_UCB1SIMO/ PM_UCB1SDA(5) 42 E7 I/O DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
P4.2/PM_UCB1SOMI/ PM_UCB1SCL(5) 43 D9 I/O DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
P4.3/PM_UCB1CLK/ PM_UCA1STE(5) 44 D8 I/O DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Clock signal input – USCI_B1 SPI slave mode
Default mapping: Clock signal output – USCI_B1 SPI master mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
P4.4/PM_UCA1TXD/ PM_UCA1SIMO(5) 45 D7 I/O DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
P4.5/PM_UCA1RXD/ PM_UCA1SOMI(5) 46 C9 I/O DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
P4.6/PM_UCA3TXD/ PM_UCA3SIMO(5) 47 C8 I/O DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Transmit data – USCI_A3 UART mode
Default mapping: Slave in, master out – USCI_A3 SPI mode
P4.7/PM_UCA3RXD/ PM_UCA3SOMI(5) 48 C7 I/O DVIO General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Receive data – USCI_A3 UART mode
Default mapping: Slave out, master in – USCI_A3 SPI mode
P7.0/UCA2TXD/UCA2SIMO(5) 49 B8, B9 I/O DVIO General-purpose digital I/O
Transmit data – USCI_A2 UART mode
Slave in, master out – USCI_A2 SPI mode
P7.1/UCA2RXD/UCA2SOMI(5) 50 A9 I/O DVIO General-purpose digital I/O
Receive data – USCI_A2 UART mode
Slave out, master in – USCI_A2 SPI mode
P7.2/UCB2CLK/UCA2STE(5) 51 B7 I/O DVIO General-purpose digital I/O
Clock signal input – USCI_B2 SPI slave mode
Clock signal output – USCI_B2 SPI master mode
Slave transmit enable – USCI_A2 SPI mode
P7.3/UCB2SIMO/UCB2SDA(5) 52 A8 I/O DVIO General-purpose digital I/O
Slave in, master out – USCI_B2 SPI mode
I2C data – USCI_B2 I2C mode
P7.4/UCB2SOMI/UCB2SCL(5) 53 A7 I/O DVIO General-purpose digital I/O
Slave out, master in – USCI_B2 SPI mode
I2C clock – USCI_B2 I2C mode
P7.5/UCB2STE/UCA2CLK(5) 54 A6 I/O DVIO General-purpose digital I/O
Slave transmit enable – USCI_B2 SPI mode
Clock signal input – USCI_A2 SPI slave mode
Clock signal output – USCI_A2 SPI master mode
BSLEN(5) 55 B6 I DVIO BSL enable with internal pulldown
RST/NMI(5) 56 A5 I DVIO Reset input active low(7)(8)
Nonmaskable interrupt input(7)
P5.2/XT2IN 57 B5 I/O DVCC General-purpose digital I/O
Input terminal for crystal oscillator XT2(9)
P5.3/XT2OUT 58 B4 I/O DVCC General-purpose digital I/O
Output terminal of crystal oscillator XT2
TEST/SBWTCK(10) 59 A4 I DVCC Test mode pin – Selects four wire JTAG operation
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
PJ.0/TDO(11) 60 C5 I/O DVCC General-purpose digital I/O
JTAG test data output port
PJ.1/TDI/TCLK(11) 61 C4 I/O DVCC General-purpose digital I/O
JTAG test data input or test clock input
PJ.2/TMS(11) 62 A3 I/O DVCC General-purpose digital I/O
JTAG test mode select
PJ.3/TCK(11) 63 B3 I/O DVCC General-purpose digital I/O
JTAG test clock
RSTDVCC/SBWTDIO(11) 64 A2 I/O DVCC Reset input active low(12)
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
Reserved N/A  (13) Reserved
QFN Pad Pad N/A QFN package pad. Connection to VSS recommended.
(1) I = input, O = output
(2) N/A = not available
(3) When in crystal bypass mode, XIN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC or DVSS to DVIO. In this case, the pin must be configured properly for the intended input swing.
(4) VCORE is for internal use only. No external current loading is possible. VCORE should be connected only to the recommended capacitor value, CVCORE (see Section 8.3).
(5) This pin function is supplied by DVIO. See Section 8.8 for input and output requirements.
(6) The voltage on DVIO is not supervised or monitored.
(7) This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, the input swing levels from DVSS to DVIO are required.
(8) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(9) When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to DVCC or DVSS to DVIO. In this case, the must pin be configured properly for the intended input swing.
(10) See Section 9.5.1 and Section 9.6 for use with BSL and JTAG functions, respectively.
(11) See Section 9.6 for use with JTAG function.
(12) This nonconfigurable reset resides on the DVCC supply domain and has an internal pullup to DVCC. When driven from external, input swing levels from DVSS to DVCC are required. This reset must be used for Spy-Bi-Wire communication and is not the same RST/NMI reset as found on other devices in the MSP430 family. Refer to Section 9.5.1 and Section 9.6 for details regarding the use of this pin.
(13) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.