ZHCSJ52A December   2019  – August 2021 LP875701-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1 Multi-Phase DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Multiphase Switcher Configurations
        3. 7.3.1.3 Buck Converter Load-Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 GPIO Signal Operation
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1.       53
        2. 7.6.1.1  DEV_REV
        3. 7.6.1.2  OTP_REV
        4. 7.6.1.3  BUCK0_CTRL1
        5. 7.6.1.4  BUCK0_DELAY
        6. 7.6.1.5  GPIO2_DELAY
        7. 7.6.1.6  GPIO3_DELAY
        8. 7.6.1.7  RESET
        9. 7.6.1.8  CONFIG
        10. 7.6.1.9  INT_TOP1
        11. 7.6.1.10 INT_TOP2
        12. 7.6.1.11 INT_BUCK_0_1
        13. 7.6.1.12 INT_BUCK_2_3
        14. 7.6.1.13 TOP_STAT
        15. 7.6.1.14 BUCK_0_1_STAT
        16. 7.6.1.15 BUCK_2_3_STAT
        17. 7.6.1.16 TOP_MASK1
        18. 7.6.1.17 TOP_MASK2
        19. 7.6.1.18 BUCK_0_1_MASK
        20. 7.6.1.19 BUCK_2_3_MASK
        21. 7.6.1.20 SEL_I_LOAD
        22. 7.6.1.21 I_LOAD_2
        23. 7.6.1.22 I_LOAD_1
        24. 7.6.1.23 PGOOD_CTRL1
        25. 7.6.1.24 PGOOD_CTRL2
        26. 7.6.1.25 PGOOD_FLT
        27. 7.6.1.26 PLL_CTRL
        28. 7.6.1.27 PIN_FUNCTION
        29. 7.6.1.28 GPIO_CONFIG
        30. 7.6.1.29 GPIO_IN
        31. 7.6.1.30 GPIO_OUT
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Input Capacitor Selection
        3. 8.2.1.3 Output Capacitor Selection
        4. 8.2.1.4 Snubber Components
        5. 8.2.1.5 Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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7.3.5 Enable and Disable Sequences

The LP875701-Q1 device supports start-up and shutdown sequencing with programmable delay for the regulator output using one EN1, EN2, or EN3 control signal. The regulator is selected for delayed control with:

  • EN_BUCK0 = 1 (in BUCK0_CTRL1 register)
  • EN_PIN_CTRL0 = 1 (in BUCK0_CTRL1 register)
  • The ENABLE pin for control is selected with BUCK0_EN_PIN_SELECT[1:0] (in BUCK0_CTRL1 register)
  • The delay from rising edge of ENx signal to the regulator enable is set by BUCK0_STARTUP_DELAY[3:0] bits (in BUCK0_DELAY register) and
  • The delay from falling edge of ENx signal to the regulator disable is set by BUCK0_SHUTDOWN_DELAY[3:0] bits (in BUCK0_DELAY register)

There are four time steps available for start-up and shutdown sequences. The delay times are selected with DOUBLE_DELAY bit in CONFIG register and HALF_DELAY bit in PGOOD_CTRL2 register as shown in Table 7-4.

Table 7-4 Start-Up and Shutdown Delays
0_STARTUP_DELAY or
0_SHUTDOWN_DELAY		DOUBLE_DELAY = 0h
HALF_DELAY = 1h		DOUBLE_DELAY = 1h
HALF_DELAY = 1h		DOUBLE_DELAY = 0h
HALF_DELAY = 0h		DOUBLE_DELAY = 1h
HALF_DELAY = 0h
0h0 ms0 ms0 ms0 ms
1h0.32 ms0.64 ms1 ms2 ms
2h0.64 ms1.28 ms2 ms4 ms
3h0.96 ms1.92 ms3 ms6 ms
4h1.28 ms2.56 ms4 ms8 ms
5h1.6 ms3.2 ms5 ms10 ms
6h1.92 ms3.84 ms6 ms12 ms
7h2.24 ms4.48 ms7 ms14 ms
8h2.56 ms5.12 ms8 ms16 ms
9h2.88 ms5.76 ms9 ms18 ms
Ah3.2 ms6.4 ms10 ms20 ms
Bh3.52 ms7.04 ms11 ms22 ms
Ch3.84 ms7.68 ms12 ms24 ms
dh4.16 ms8.32 ms13 ms26 ms
Eh4.48 ms8.96 ms14 ms28 ms
Fh4.8 ms9.6 ms15 ms30 ms

An example of start-up and shutdown sequences is shown in Figure 7-6 and Figure 7-7. The start-up and shutdown delays for the master buck regulator BUCK0 regulator is 1 ms and 4 ms . The delay settings are used only for enable/disable control with EN1, EN2, EN3 signals

GUID-A670CF4E-B13B-42BA-A9A0-51DF791C6CFB-low.gifFigure 7-6 Typical Start-Up and Shutdown Sequencing
GUID-8B3975D4-A78B-4A9D-8469-4170B00542D8-low.gifFigure 7-7 Start-Up and Shutdown Sequencing With Short ENx Low and High Periods