Unless otherwise noted, test conditions are the same as in Typical Characteristics. 156.25-MHz output (APLL1) on OUT3 and 155.52 MHz output (APLL2) on OUT4 running simultaneously to demonstrate minimal coupling between the PLL domains and minimal degradation in phase noise and jitter. Device operating in DPLL Mode with Cascaded APLL2. AC-LVPECL outputs measured.