ZHCSID6A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
APLL2 has a cascaded primary R divider (÷3 to ÷6) and secondary R divider (÷1 to ÷32) to divide-down the VCO1 clock to meet the maximum APLL2 PFD frequency specification in Cascaded APLL2 mode. The dividers can also be used to operate APLL2 in integer mode or avoid near-integer spurs in fractional mode.