ZHCSK16A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay, and half step.
BIT | NAME | POR DEFAULT | DESCRIPTION | |
---|---|---|---|---|
7 | NA | 0 | Reserved | |
6 | DCLKoutX_HS | 0 | Sets the device clock half step value. Half step must be zero (0) for a divide of 1.
0: 0 cycles 1: -0.5 cycles |
|
5 | SDCLKoutY_MUX | 0 | Sets the input the the SDCLKoutY outputs.
0: Device clock output 1: SYSREF output |
|
4:1 | SDCLKoutY_DDLY | 0 | Sets the number of VCO cycles to delay the SDCLKout by. | |
Field Value | Delay Cycles | |||
0 (0x00) | Bypass | |||
1 (0x01) | 2 | |||
2 (0x02) | 3 | |||
... | ... | |||
10 (0x0A) | 11 | |||
11 to 15 (0x0B to 0x0F) | Reserved | |||
0 | SDCLKoutY_HS | 0 | Sets the SYSREF clock half step value.
0: 0 cycles 1: -0.5 cycles |