ZHCSK16A October 2017 – July 2019 LMK04228
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
CURRENT CONSUMPTION | |||||||
ICC_PD | Power-down supply current | 1 | 3 | mA | |||
ICC_CLKS | Supply current(2) | 14 LVDS clocks enabled
PLL1 and PLL2 locked. |
485 | mA | |||
CLKin0/0*, CLKin1/1*, AND CLKin2/2* INPUT CLOCK SPECIFICATIONS | |||||||
fCLKin | Clock input frequency | 0.001 | 400 | MHz | |||
SLEWCLKin | Clock input slew rate(3) | 20% to 80% | 0.15 | 0.5 | V/ns | ||
VIDCLKin | Clock input
differential input voltage(1) Figure 2 |
AC-coupled | 0.125 | 1.55 | |V| | ||
VSSCLKin | 0.25 | 3.1 | Vpp | ||||
VCLKin | Clock input
single-ended input voltage |
AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground CLKinX_TYPE = 0 (Bipolar) |
0.25 | 2.4 | Vpp | ||
AC-coupled to CLKinX;
CLKinX* AC-coupled to Ground CLKinX_TYPE = 1 (MOS) |
0.35 | 2.4 | |||||
VCLKinX-offset| | DC offset voltage between
CLKinX/CLKinX* (CLKinX* – CLKinX) |
Each pin AC-coupled, CLKin0/1/2
CLKinX_TYPE = 0 (Bipolar) |
0 | |mV| | |||
Each pin AC-coupled, CLKin0/1
CLKinX_TYPE = 1 (MOS) |
55 | ||||||
DC offset voltage between
CLKin2/CLKin2* (CLKin2* – CLKin2) |
Each pin AC-coupled
CLKinX_TYPE = 1 (MOS) |
20 | |||||
VCLKin- VIH | High input voltage | DC-coupled to CLKinX;
CLKinX* AC-coupled to Ground CLKinX_TYPE = 1 (MOS) |
2 | VCC | V | ||
VCLKin- VIL | Low input voltage | 0 | 0.4 | V | |||
PLL1 SPECIFICATIONS | |||||||
fPD1 | PLL1 phase detector frequency | 40 | MHz | ||||
ICPout1SOURCE | PLL1 charge
pump source current(4) |
VCPout1 = VCC/2, PLL1_CP_GAIN = 0 | 50 | µA | |||
VCPout1 = VCC/2, PLL1_CP_GAIN = 1 | 150 | ||||||
VCPout1 = VCC/2, PLL1_CP_GAIN = 2 | 250 | ||||||
… | … | ||||||
VCPout1 = VCC/2, PLL1_CP_GAIN = 14 | 1450 | ||||||
VCPout1 = VCC/2, PLL1_CP_GAIN = 15 | 1550 | ||||||
ICPout1SINK | PLL1 charge
pump sink current(4) |
VCPout1=VCC/2, PLL1_CP_GAIN = 0 | –50 | µA | |||
VCPout1=VCC/2, PLL1_CP_GAIN = 1 | –150 | ||||||
VCPout1=VCC/2, PLL1_CP_GAIN = 2 | –250 | ||||||
… | … | ||||||
VCPout1=VCC/2, PLL1_CP_GAIN = 14 | –1450 | ||||||
VCPout1=VCC/2, PLL1_CP_GAIN = 15 | –1550 | ||||||
ICPout1%MIS | Charge pump
sink / source mismatch |
VCPout1 = VCC/2, T = 25 °C | 1% | 10% | |||
ICPout1VTUNE | Magnitude of charge pump current variation vs. charge pump voltage | 0.5 V < VCPout1 < VCC – 0.5 V
TA = 25°C |
4% | ||||
ICPout1%TEMP | Charge pump current vs. temperature variation | 4% | |||||
ICPout1 TRI | Charge pump TRI-STATE leakage current | 0.5 V < VCPout < VCC – 0.5 V | 5 | nA | |||
PN10kHz | PLL 1/f noise at 10-kHz offset. Normalized to 1-GHz output frequency | PLL1_CP_GAIN = 350 µA | –117 | dBc/Hz | |||
PLL1_CP_GAIN = 1550 µA | –118 | ||||||
PN1Hz | Normalized phase noise contribution | PLL1_CP_GAIN = 350 µA | –221.5 | dBc/Hz | |||
PLL1_CP_GAIN = 1550 µA | –223 | ||||||
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS | |||||||
fOSCin | PLL2 reference input(6) | 500 | MHz | ||||
SLEWOSCin | PLL2 reference clock minimum slew rate on OSCin (3) | 20% to 80% | 0.15 | 0.5 | V/ns | ||
VOSCin | Input voltage for OSCin or OSCin*
|
AC-coupled; single-ended
(Unused pin AC-coupled to GND) |
0.2 | 2.4 | Vpp | ||
VIDOSCin | Differential voltage swing
See Figure 2 |
AC-coupled | 0.2 | 1.55 | |V| | ||
VSSOSCin | 0.4 | 3.1 | Vpp | ||||
|VOSCin-offset| | DC offset voltage between
OSCin/OSCin* (OSCinX* - OSCinX) |
Each pin AC-coupled | 20 | |mV| | |||
fdoubler_max | Doubler input frequency (5) | EN_PLL2_REF_2X = 1(7);
OSCin duty cycle 40% to 60% |
155 | MHz | |||
CRYSTAL OSCILLATOR MODE SPECIFICATIONS | |||||||
FXTAL | Crystal frequency range | Fundamental mode crystal
ESR = 200 Ω (10 to 30 MHz) ESR = 125 Ω (30 to 40 MHz) |
10 | 40 | MHz | ||
CIN | Input capacitance of OSCin port | –40°C to +85°C | 1 | pF | |||
PLL2 PHASE DETECTOR AND CHARGE PUMP SPECIFICATIONS | |||||||
fPD2 | Phase detector frequency (5) | 155 | MHz | ||||
ICPoutSOURCE | PLL2 charge pump source current (4) | VCPout2=VCC/2, PLL2_CP_GAIN = 0 | 100 | µA | |||
VCPout2=VCC/2, PLL2_CP_GAIN = 1 | 400 | ||||||
VCPout2=VCC/2, PLL2_CP_GAIN = 2 | 1600 | ||||||
ICPoutSINK | PLL2 charge pump sink current (4) | VCPout2=VCC/2, PLL2_CP_GAIN = 0 | –100 | µA | |||
VCPout2=VCC/2, PLL2_CP_GAIN = 1 | –400 | ||||||
VCPout2=VCC/2, PLL2_CP_GAIN = 2 | –1600 | ||||||
ICPout2%MIS | Charge pump sink/source mismatch | VCPout2=VCC/2, TA = 25°C | 1% | 10% | |||
ICPout2VTUNE | Magnitude of charge pump current vs. charge pump voltage variation | 0.5 V < VCPout2 < VCC – 0.5 V
TA = 25°C |
4% | ||||
ICPout2%TEMP | Charge pump current vs. temperature variation | 4% | |||||
ICPout2TRI | Charge pump leakage | 0.5 V < VCPout2 < VCC – 0.5 V | 10 | nA | |||
PN10kHz | PLL 1/f noise at 10-kHz offset(8). Normalized to
1-GHz output frequency |
PLL2_CP_GAIN = 1600 µA | –120 | dBc/Hz | |||
PN1Hz | Normalized phase noise contribution(9) | PLL2_CP_GAIN = 400 µA | –222.5 | dBc/Hz | |||
PLL2_CP_GAIN = 1600 µA | –224 | ||||||
INTERNAL VCO SPECIFICATIONS | |||||||
fVCO | LMK04228 VCO tuning range | VCO0 | 2370 | 2630 | MHz | ||
VCO1 | 2920 | 3080 | |||||
KVCO | LMK04228 fine tuning sensitivity | LMK04228 VCO0 at 2370 MHz(10) | 17 | MHz/V | |||
LMK04228 VCO0 at 2630 MHz(10) | 27 | ||||||
LMK04228 VCO1 at 2920 MHz(10) | 17 | ||||||
LMK04228 VCO1 at 3080 MHz(10) | 23 | ||||||
|ΔTCL| | Allowable temperature drift for continuous lock(11) | After programming for lock, no changes to output configuration are permitted to assure continuous lock | 125 | °C | |||
NOISE FLOOR | |||||||
L(f)CLKout | LMK04228, VCO0, noise floor
20-MHz offset(12) |
245.76 MHz | LVDS | –156.3 | dBc/Hz | ||
LVPECL16 with 240 Ω | –161.6 | ||||||
LVPECL20 with 240 Ω | –162.5 | ||||||
L(f)CLKout | LMK04228, VCO1, noise floor
20-MHz offset(12) |
245.76 MHz | LVDS | –155.7 | dBc/Hz | ||
LVPECL16 with 240 Ω | –160.3 | ||||||
LVPECL20 with 240 Ω | –161.1 | ||||||
CLKout CLOSED-LOOP PHASE NOISE SPECIFICATIONS A COMMERCIAL QUALITY VCXO(15) | |||||||
L(f)CLKout | LMK04228
VCO0 SSB phase noise(12) 245.76 MHz |
Offset = 1 kHz | –115.2 | dBc/Hz | |||
Offset = 10 kHz | –126.5 | ||||||
Offset = 100 kHz | –128.3 | ||||||
Offset = 1 MHz | –150.0 | ||||||
Offset = 10 MHz | LVDS | –157.9 | |||||
LVPECL20 with 240 Ω | –163.1 | ||||||
L(f)CLKout | LMK04228
VCO1 SSB phase noise(12) 245.76 MHz |
Offset = 1 kHz | –115.1 | dBc/Hz | |||
Offset = 10 kHz | –126.3 | ||||||
Offset = 100 kHz | –127.5 | ||||||
Offset = 1 MHz | –154.4 | ||||||
Offset = 10 MHz | LVDS | –157.9 | |||||
LVPECL20 with 240 Ω | –162.3 | ||||||
CLKout CLOSED-LOOP JITTER SPECIFICATIONS A COMMERCIAL QUALITY VCXO(15) | |||||||
JCLKout | LMK04228, VCO0
fCLKout = 245.76 MHz Integrated RMS jitter (12) |
LVDS, BW = 100 Hz to 20 MHz | 256 | fs rms | |||
LVDS, BW = 12 kHz to 20 MHz | 183 | ||||||
LVPECL20 /w 240 Ω,
BW = 100 Hz to 20 MHz |
254 | ||||||
LVPECL20 /w 240 Ω,
BW = 12 kHz to 20 MHz |
176 | ||||||
LMK04228, VCO1
fCLKout = 245.76 MHz Integrated RMS jitter (12) |
LVDS, BW = 100 Hz to 20 MHz | 246 | |||||
LVDS, BW = 12 kHz to 20 MHz | 162 | ||||||
LVPECL16 with 240 Ω,
BW = 100 Hz to 20 MHz |
245 | ||||||
LVPECL20 with 240 Ω,
BW = 12 kHz to 20 MHz |
156 | ||||||
DEFAULT POWER ON RESET CLOCK OUTPUT FREQUENCY | |||||||
fCLKout-startup | Default output clock frequency at device power on (16)(17) | LMK04228 | 315 | MHz | |||
fOSCout | OSCout frequency | See(5) | 500 | MHz | |||
CLOCK SKEW AND DELAY | |||||||
|TSKEW| | DCLKoutX to SDCLKoutY
FCLK = 245.76 MHz, RL= 100 Ω AC-coupled(13) |
Same pair, same format (14)
SDCLKoutY_MUX = 0 (device clock) |
25 | |ps| | |||
Maximum DCLKoutX or SDCLKoutY
to DCLKoutX or SDCLKoutY FCLK = 245.76 MHz, RL= 100 Ω AC-coupled |
Any pair, same format (14)
SDCLKoutY_MUX = 0 (device clock) |
50 | |||||
tsJESD204B | SYSREF to device clock setup time base reference.
See SYSREF to Device Clock Alignment to adjust SYSREF to device clock setup time as required. |
SDCLKoutY_MUX = 1 (SYSREF)
SYSREF_DIV = 30 SYSREF_DDLY = 8 (global) SDCLKoutY_DDLY = 1 (2 cycles, local) DCLKoutX_MUX = 1 (Div+DCC+HS) DCLKoutX_DIV = 30 DCLKoutX_DDLY_CNTH = 7 DCLKoutX_DDLY_CNTL = 6 DCLKoutX_HS = 0 SDCLKoutY_HS = 0 |
–80 | ps | |||
tPDCLKin0_
SDCLKout1 |
Propagation delay from CLKin0 to SDCLKout1 | CLKin0_OUT_MUX = 0 (SYSREF Mux)
SYSREF_CLKin0_MUX = 1 (CLKin0) SDCLKout1_PD = 0 SDCLKout1_DDLY = 0 (Bypass) SDCLKout1_MUX = 1 (SR) EN_SYNC = 1 LVPECL16 with 240 Ω |
0.65 | ns | |||
fADLYmax | Maximum analog delay frequency | DCLKoutX_MUX = 4 | 1250 | MHz | |||
LVDS CLOCK OUTPUTS (DCLKoutX, SDCLKoutY, AND OSCout) | |||||||
VOD | Differential output voltage | T = 25°C, DC measurement
AC-coupled to receiver input RL = 100-Ω differential termination |
395 | |mV| | |||
ΔVOD | Change in magnitude of VOD for complementary output states | –60 | 60 | mV | |||
VOS | Output offset voltage | 1.125 | 1.25 | 1.375 | V | ||
ΔVOS | Change in VOS for complementary output states | 35 | |mV| | ||||
TR / TF | Output rise time | 20% to 80%, RL = 100 Ω, 245.76 MHz | 180 | ps | |||
Output fall time | 80% to 20%, RL = 100 Ω | ||||||
ISA
ISB |
Output short-circuit current - single-ended | Single-ended output shorted to GND
T = 25°C |
–24 | 24 | mA | ||
ISAB | Output short-circuit current - differential | Complementary outputs tied together | –12 | 12 | mA | ||
LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY) | |||||||
TR / TF | 20% to 80% output rise | RL = 100 Ω, emitter resistors = 240 Ω to GND
DCLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp) |
150 | ps | |||
80% to 20% output fall time | |||||||
1600-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY) | |||||||
VOH | Output high voltage | DC Measurement
Termination = 50 Ω to VCC – 2 V |
VCC – 1.04 | V | |||
VOL | Output low voltage | VCC – 1.80 | V | ||||
VOD | Output voltage
See Figure 3 |
760 | |mV| | ||||
2000-mVpp LVPECL CLOCK OUTPUTS (DCLKoutX AND SDCLKoutY) | |||||||
VOH | Output high voltage | DC Measurement
Termination = 50 Ω to VCC – 2.3 V |
VCC – 1.09 | V | |||
VOL | Output low voltage | VCC – 2.05 | V | ||||
VOD | Output voltage
See Figure 3 |
960 | |mV| | ||||
LVCMOS CLOCK OUTPUTS (OSCout) | |||||||
fCLKout | Maximum frequency(18) | 5-pF Load | 250 | MHz | |||
VOH | Output high voltage | 1-mA Load | VCC – 0.1 | V | |||
VOL | Output low voltage | 1-mA Load | 0.1 | V | |||
IOH | Output high current (source) | VCC = 3.3 V, VO = 1.65 V | 28 | mA | |||
IOL | Output low current (sink) | VCC = 3.3 V, VO = 1.65 V | 28 | mA | |||
DUTYCLK | Output duty cycle(20) | VCC/2 to VCC/2,
FCLK = 100 MHz, T = 25°C |
50% | ||||
TR | Output rise time | 20% to 80%, RL = 50 Ω, CL = 5 pF | 400 | ps | |||
TF | Output fall time | 80% to 20%, RL = 50 Ω, CL = 5 pF | 400 | ps | |||
DIGITAL OUTPUTS (CLKin_SELX, Status_LDX, AND RESET/GPO) | |||||||
VOH | High-level output voltage | IOH = –500 µA
CLKin_SELX_TYPE = 3 or 4 Status_LDX_TYPE = 3 or 4 RESET_TYPE = 3 or 4 |
VCC – 0.4 | V | |||
VOL | Low-level output voltage | IOL = 500 µA
CLKin_SELX_TYPE = 3, 4, or 6 Status_LDX_TYPE = 3, 4, or 6 RESET_TYPE = 3, 4, or 6 |
0.4 | V | |||
DIGITAL OUTPUT (SDIO) | |||||||
VOH | High-level output voltage | IOH = –500 µA ; during SPI read.
SDIO_RDBK_TYPE = 0 |
VCC – 0.4 | V | |||
VOL | Low-level output voltage | IOL = 500 µA ; during SPI read.
SDIO_RDBK_TYPE = 0 or 1 |
0.4 | V | |||
DIGITAL INPUTS (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, OR CS*) | |||||||
VIH | High-level input voltage | 1.2 | VCC | V | |||
VIL | Low-level input voltage | 0.4 | V | ||||
DIGITAL INPUTS (CLKinX_SEL) | |||||||
IIH | High-level input current
VIH = VCC |
CLKin_SELX_TYPE = 0,
(high impedance) |
–5 | 5 | µA | ||
CLKin_SELX_TYPE = 1 (pullup) | –5 | 5 | |||||
CLKin_SELX_TYPE = 2 (pulldown) | 10 | 80 | |||||
IIL | Low-level input current
VIL = 0 V |
CLKin_SELX_TYPE = 0,
(High Impedance) |
–5 | 5 | µA | ||
CLKin_SELX_TYPE = 1 (pullup) | –40 | –5 | |||||
CLKin_SELX_TYPE = 2 (pulldown) | –5 | 5 | |||||
DIGITAL INPUT (RESET/GPO) | |||||||
IIH | High-level input current
VIH = VCC |
RESET_TYPE = 2
(pulldown) |
10 | 80 | µA | ||
IIL | Low-level input current
VIL = 0 V |
RESET_TYPE = 0 (high impedance) | –5 | 5 | µA | ||
RESET_TYPE = 1 (pullup) | –40 | -5 | |||||
RESET_TYPE = 2 (pulldown) | –5 | 5 | |||||
DIGITAL INPUTS (SYNC) | |||||||
IIH | High-level input current | VIH = VCC | 25 | µA | |||
IIL | Low-level input current | VIL = 0 V | –5 | 5 | |||
DIGITAL INPUTS (SCK, SDIO, CS*) | |||||||
IIH | High-level input current | VIH = VCC | –5 | 5 | µA | ||
IIL | Low-level input current | VIL = 0 | –5 | 5 | µA | ||
DIGITAL INPUT TIMING | |||||||
tHIGH | RESET pin held high for device reset | 25 | ns |