Calculating the value of the output dividers is simple due to the architecture of the LMK03806. That is, the clock output dividers allow for even and odd output divide values from 2 to 1045. The procedure for determining the PLL and clock output divider values for a set of clock output frequencies is straightforward.

1. Calculate the least common multiple (LCM) of the clock output frequencies.
2. Determine which VCO frequency will support the target clock output frequencies given the LCM.
3. Determine the clock output divide values based on VCO frequency.
4. Determine the PLL divider values – VCO_DIV, PLL_P, PLL_N, and PLL_R – to allow the VCO frequency to lock to the OSCin frequency. For best in-band PLL noise, try to maximize the PLL phase detector frequency by using the smallest PLL divider values and enabling the PLL doubler.

For example, given the following target output frequencies: 156.25 MHz, 125 MHz, 100 MHz, and 25 MHz with a OSCin frequency of 20 MHz:

1. Determine the LCM of the three frequencies. LCM(156.25, 125, 100, 25) = 2500 MHz. The LCM frequency is the lowest frequency for which all of the target output frequencies are integer divisors of the LCM. Note: if there is one frequency which causes the LCM to be very large, greater than 2.6 GHz for example, determine if there is a single frequency requirement which causes this. It may be possible to select the crystal frequency to satisfy this frequency requirement through OSCout or CLKout6/7/8/9 driven by OSCin. In this way it is possible to get non-integer related frequencies at the outputs.
2. Multiply the LCM frequency by an integer value that causes the product (LCM × X) to fall into the valid VCO frequency range from 2370 to 2600 MHz. In this case, the LCM frequency of 2500 MHz is already within the VCO frequency.
3. Continuing the example by using a VCO frequency of 2500 MHz, the CLKout dividers can be calculated by simply dividing the VCO frequency by the output frequency. To output 156.25 MHz, 125 MHz, 100 MHz, and 25 MHz, the output dividers will be 16, 20, 25, and 100, respectively.
   1. 2500 MHz / 156.25 MHz = 16
   2. 2500 MHz / 125 MHz = 20
   3. 2500 MHz / 100 MHz = 25
   4. 2500 MHz / 25 MHz = 100
4. The PLL must be locked to its input reference. Refer to Configuring the PLL for more information on this topic. By programming the clock output dividers and the PLL dividers, the VCO can be locked to 2500 MHz and the clock outputs dividers can each divide-down the VCO frequency to the achieve the target output frequencies.

Refer to Application Note AN-1865, Frequency Synthesis and Planning for PLL Architectures (SNAA061) for more information on this topic and LCM calculations.