7.3.1 Power Amplifier Synchronization (TX1)

The TX1/TORCH/GPIO1 pin has a triple function. With the Configuration Register 1 Bit [7] = 0 (default) TX1/TORCH/GPIO1 is a power-amplifier-synchronization input. This mode is designed to reduce the flash LED current when TX1 is pulled high (active high polarity) or low (active low polarity). When the LM3559 is engaged in a flash event and the TX1/TORCH pin is pulled high, both LED1 and LED2 are forced into torch mode at the programmed torch current setting. If TX1 is then pulled low before the flash pulse terminates, the LED current returns to the previous flash current level. At the end of the flash timeout, whether the TX1/TORCH pin is high or low, the current sources turn off.

The polarity of the TX1 input can be changed from active high to active low by writing a 0 to bit [5] of Configuration Register 1. With this bit set to 0 the LM3559 is forced into torch mode when TX1/TORCH is pulled low. Figure 25 details the functionality of the TX1 interrupt.

Figure 25. TX1 or TX2 Interrupt Event

Figure 26. Hardware-Torch Mode

7.3.2 Input Voltage Flash Monitor Fault

The V_IN flash monitor flag (bit [6] of the Flags Register reads back a 1 when the input voltage flash monitor is enabled and V_IN falls below the programmed V_IN flash monitor threshold. This flag must be read back in order to resume normal operation after the LED current has been forced to the lower flash current setting.

7.3.3 Independent LED Control

Bits [4:3] of the enable register provide for independent turnon and turnoff of the LED1 or LED2 current sources. The LED current is adjusted by writing to the Torch Brightness or Flash Brightness Registers. Both the Torch Brightness and the Flash Brightness Register provide for independent current programming for the LED currents in either LED1 or LED2. (See Torch Brightness Register and Flash Brightness Register descriptions.)

7.3.4 Hardware Torch

With Configuration Register 1 Bit [7] = 1, TX1/TORCH is configured as a hardware-torch-mode enable. In this mode (TORCH mode), a high at TX1/TORCH turns on the LED current at the programmed torch current setting. The STROBE input and I²C-enabled flash takes precedence over torch mode. In hardware-torch mode, both LED1 and LED2 current sources turn off after a flash event ,and Configuration Register 1 Bit [7] is reset to 0. In this situation, to re-enter torch mode via hardware torch, the hardware-torch enable bit (Configuration Register 1 Bit [7]) must be reset to 1. Figure 26 details the functionality of the TX1/TORCH/GPIO1 input.

7.3.5 Fault Protections

7.3.5.4 Indicator LED/Thermistor (LEDI/NTC)

The LEDI/NTC pin serves a dual function, either as a programmable LED message indicator driver, or as a comparator input for negative temperature coefficient (NTC) thermistors.

7.3.5.4.1 Message Indicator Current Source (LEDI/NTC)

LEDI/NTC is configured as a message indicator current source by setting Configuration Register 1 bit [4] = 0. The indicator current source is enabled/disabled via Enable Register bit [6]. Enable Register bit [7] programs the message indictor for blinking mode. When the message indicator is set for blinking mode the pattern programmed into the Indicator Register and Indicator Blinking Register is sent to the message indicator current source.

The Indicator Blinking Register controls the following (see Table 17):

1. Number of blank periods (BLANK#. This has 16 settings. t_BLANK = t_ACTIVE × BLANK# , where t_ACTIVE = t_PERIOD × PERIOD#
2. Pulse width (t_PULSE) has 16 settings between 0 and 480 ms in steps of 32 ms. The pulse width is the duration which the indicator current is at its programmed set point at the end of the ramp-up time.

The Indicator Register controls the following (see Table 16):

1. Indicator current level (I_IND). There are 8 message indicator current levels from 2.25 mA to 18 mA in steps of 2.25 mA.
2. Number of periods (PERIOD#). This has 8 steps. A period (t_PERIOD) is found by (t_PERIOD = t_R + t_F + 2 × t_PULSE). (See Figure 27 for indicator timing).
3. Ramp times (t_R or t_F) for turnon and turnoff of the indicator current source. Four programmable times of 78 ms, 156 ms, 312 ms, and 624 ms are available. The ramp times apply for both ramp-up and ramp-down and are not independently changeable.

Figure 27. Message Indicator Timing Diagram

7.3.5.4.1.1 Message Indicator Example 1 (Single Pulse With Dead Time):

As an example, to set up the message indicator for a 312-ms ramp-up and ramp-down, 192 ms pulse width, and 1 pulse followed by a 5-s delay. The indicator settings will be as follows. t_R = t_F = 312 ms, t_WIDTH = 192 ms (t_PERIOD = 312 ms × 2 + 192 ms × 2 = 1016 ms). BLANK# setting will be: 5 s / 1016 ms × 1 (PERIOD# = 1). Giving a BLANK# setting of 5. The resulting waveform appears as shown in Figure 28.

Figure 28. Message Indicator Example 1

7.3.5.4.1.2 Message Indicator Example 2 (Multiple Pulses With Dead Time):

Another example has the same t_R, t_F, t_PULSE, and t_BLANK times as before, but this time the PERIOD# is set to 3. Now the t_ACTIVE time is t_PERIOD × 3 = 1016 ms × 3 = 3048 ms. This results in a blank time of t_BLANK = t_ACTIVE × BLANK# = 3.048 s × 5 = 15.24 s (see Figure 29).

Figure 29. Message Indicator Example 2

7.3.5.4.1.3 Updating The Message Indicator

The best way to update the message indicator is to disable the message indicator output via the Enable Register bit [7], write the new sequence to the Indicator Register and/or Indicator Blinking Register, and then re-enable the message indicator. Updating the Indicator Registers on the fly can lead to long delays between pattern changes. This is especially true if the PERIOD# or BLANK# setting is changed from a high setting to a lower setting.

7.3.6 Input Voltage (V_IN ) Monitor

The LM3559 has an internal comparator at IN that monitors the input voltage and can force the LED current into torch mode or into shutdown, if V_IN falls below the programmable V_IN monitor threshold. Bit 0 in the V_IN Monitor Register enables or disables this feature. Bits [2:1] of the VIN Monitor Register program the 4 adjustable thresholds of 2.9 V, 3 V, 3.1 V, and 3.2 V. Bit 3 in Configuration Register 2 selects whether an undervoltage event forces torch mode or forces the LEDs off. See Table 13 for additional information. When the V_IN monitor is active and V_IN falls below the programmed VIN Monitor threshold, the active current sources (LED1 and/or LED2) either turns off or is forced into the torch current setting. To reset the LED current to its previous level, V_IN must go above the V_IN monitor threshold and the Flags Register must be read back. See Figure 30 for the V_IN monitor timing waveform.

To avoid noise from falsely triggering the V_IN monitor, this mode incorporates a 250 µs deglitch timer. With the V_IN monitor active, V_IN must go below the VIN monitor threshold (V_{IN_TH}) and remain below it for 250 µs before the LEDs are forced into torch mode (or shut down) and the V_IN monitor flag is written.

Figure 30. V_IN Monitor Waveform

7.3.7 V_IN Flash Monitor (Flash Current Rising)

A second comparator at IN is available to monitor the input voltage during the flash current turnon. Bit [3] of the VIN Monitor Register enables/disables this feature. With this bit set to 1 the V_IN flash monitor is active. Bits [5:4] of the VIN Monitor Register program the 4 selectable thresholds of (2.9 V, 3 V, 3.1 V, and 3.2 V). The feature operates as follows: during flash current turnon the active current sources (LED1 and/or LED2) transition through each of the lower flash and torch current levels until the target flash current is reached. With the V_IN flash monitor active, if the input voltage falls below the V_IN flash monitor threshold during the flash current turnon,the flash current is set to the level that the current ramp had risen to at the time of the undervoltage event. The V_IN flash monitor only operates during the ramping up of the flash LED current.

The V_IN flash monitor ignores the first 2 flash codes during the flash pulse turnon. As a result, if the V_IN flash monitor is enabled, and V_IN were to fall below the V_IN flash threshold as the LED current ramps up through either of the first two levels, then the flash pulse would not be halted until code #3 (168.75-mA per current source).

To avoid noise from falsely triggering the V_IN flash monitor, this mode incorporates an 8-µs deglitch timer as well as an internal analog filter at the input of the V_IN flash monitor comparator. With the V_IN flash monitor active, V_IN must go below the V_IN flash monitor threshold (V_{IN_FLASH}) and remain below it for 8 µs before the flash current ramp is halted and the V_IN flash monitor flag is written.

7.3.8 Last Flash Register

Once the V_IN flash monitor is tripped, the flash code that corresponded to the LED current at which the flash current ramp was halted is written to the Last Flash Register. The Last Flash Register is a read-only register; the lower 4 bits are available to latch the code for LED1 and the upper 4 bits to latch the code for LED2.

For example, suppose that the LM3559 device is set up for a single LED with a target flash current of 1125 mA. The V_IN flash monitor is enabled with the V_IN flash monitor threshold set to 3. V (VIN Monitor Register bits [5:4] = 0, 1). When the STROBE input is brought high, the LED current begins ramping up through the torch and flash codes at 32 µs per code. As the input current increases, the input voltage at the device IN pin begins to fall due to the source impedance of the battery. By the time the LED current has reached 900 mA (code 0x77 or 450 mA per current source), V_IN falls below 3 V. The V_IN flash monitor then stops the flash current ramp and the device continues to proceed with the flash pulse, but at 900 mA instead of 1125 mA. Figure 31 details this sequence.

Figure 31. V_IN Flash Monitor Example

7.3.9 LED Voltage Monitor

The LM3559 includes a 4-bit ADC which monitors the LED forward voltage (V_LED) and stores the digitized value in bits [3:0] of the VLED Monitor Register. The highest voltage of VLED1 or VLED2 is automatically sensed and that becomes the sample point for the ADC. Bit 5, the ADC shutdown bit, enables or disables the ADC with the default state set to enable (bit [5] = 0).

7.3.10 ADC Delay

The ADC Delay Register provides for a programmable delay from 250 µs to 8 ms, in steps of 250 µs. This delay is the delay from when the EOC bit goes low to when the V_LED monitor samples the LED voltage. In automatic mode the EOC bit goes low when the Flash LED current hits its target. In manual mode the EOC bit goes low at the end of a readback of the VLED Monitor Register (or when the manual mode bit (bit 4) is re-written with a 1). Figure 32 and Figure 33 detail the timing of the VLED Monitor for both automatic mode and manual mode.

Figure 32. V_LED Monitor Automatic Mode

Figure 33. V_LED Monitor Manual Mode

7.3.11 Flags Register and Fault Indicators

Eight fault flags are available in the LM3559. These include: a flash timeout, a thermal shutdown, an LED failure flag (LEDF), an LED thermal flag (NTC), a V_IN monitor flag, and a V_IN flash monitor flag. Additionally, two LED interrupt flag bits (TX1 interrupt and TX2 interrupt) are set when the corresponding interrupt is activated. Reading back a 1 indicates the flagged event has happened. A read of the Flags Register resets these bits.

7.4.1 Start-Up (Enabling the Device)

Turnon of the LM3559 is done through bits [1:0] of the Enable Register. Bits [1:0] enable the device in torch mode, flash mode, or privacy Indicate mode. Additionally, bit 6 enables the message indicator at the LEDI/NTC pin. On start-up, when V_OUT is less than V_IN, the internal synchronous PFET turns on as a current source and delivers 350 mA to the output capacitor. During this time both current sources (LED1, and LED2) are off. When the voltage across the output capacitor reaches 2.2 V the active current sources can turn on. At turnon the current sources step through each flash and torch level until their target LED current is reached (32 µs/step). This gives the device a controlled turnon and limits inrush current from the V_IN supply.

7.4.2 Pass Mode

At turnon, when the output voltage charges up to (V_IN – 150 mV), the device operates in either pass mode or boost mode, depending upon the voltage difference between V_OUT and V_LED. If the voltage difference between V_OUT and V_LED is less than 270 mV, the device operates in boost mode. If the difference between V_OUT and V_LED is greater than 270 mV, the device operates in pass mode. In pass mode the boost converter stops switching, and the synchronous PFET turns fully on, bringing V_OUT up to V_IN – I_IN × R_PMOS (R_PMOS = 80 mΩ). In pass mode the inductor current is not limited by the peak current limit. In this situation the output current must be limited to 3 A.

7.4.3 Flash Mode

In flash mode the LED current sources (LED1 and LED2) each provide 16 different current levels from typically 56.25 mA (total) to 1.8 A (total) in steps of 56.25 mA. The flash currents are adjusted via the Flash Brightness Register. Flash mode is activated by writing a 1, 1 to bits [1:0] of the Enable Register or by enabling the hardware flash input (STROBE) via bit [2] of Configuration Register 1 and then pulling the STROBE pin high (high polarity). Once the flash sequence is activated both current sinks (LED1 and LED2) ramp up to their programmed flash current level by stepping through all torch and flash levels (32 µs/step) until the programmed current is reached.

Bit [5] of the Enable Register (STROBE Level/Edge bit) determines how the flash pulse terminates. With the Level/Edge bit = 1 the flash current only terminates when it reaches the end of the flash timeout period. With the level/edge bit = 0, flash mode can be terminated by pulling STROBE low, programming bits [1:0] of the Enable Register with 0,0, or by allowing the flash timeout period to elapse. If the level/edge bit = 0 and STROBE is toggled before the end of the flash timeout period the timeout period resets. Figure 34 and Figure 35 detail the flash pulse termination for the different level/edge bit settings.

Figure 34. LED Current for Strobe (Level Triggered, Enable Register Bit [5] = 0)
Strobe Goes Low Before the End of the Programmed Timeout Duration

Figure 35. LED Current for Strobe (Edge Triggered, Enable Register Bit [5] = 1)

After the flash pulse terminates; either by a flash timeout, pulling STROBE low or disabling it via the I²C-compatible interface, LED1 and LED2 turn completely off. This happens even when torch is enabled via the I²C-compatible interface, and the flash pulse is turned on by toggling STROBE. After a flash event ends, the EN1, EN0 bits (bits [1:0] of the Enable Register) are automatically reset with 0, 0. The exception occurs when the privacy terminate bit is low (bit [3]) in the Privacy Register. In this case, the specific current source that is enabled for privacy mode turns back on after the flash pulse if privacy mode had been enabled before the flash pulse.

7.4.4 Torch Mode

In torch mode the current sources LED1 and LED2 each provide 8 different current levels (Table 3). Torch mode is activated by setting Enable Register bits [1:0] to (1, 0). Once torch mode is enabled, the current sources ramp up to the programmed torch current level by stepping through all of the torch currents at (32 µs/step) until the programmed torch current level is reached.

7.4.5 Privacy-Indicate Mode

The current sources (LED1 and/or LED2) can also be used as a privacy indicator before and after flash mode. Privacy-indicate mode is enabled by setting the Enable Register bit [1:0] to (0,1). Additionally, the Privacy Register contains the bits to select which current source to use as the privacy indicator (either LED1, LED2, or both), whether or not the privacy-indicate mode turns off at the end of the flash pulse, and contains the 8 intensity levels for the privacy indicator.

The intensity of the LEDs in privacy indicate mode is set by PWM’ing the lowest torch current level (28.125 mA). Bits [2:0] of the Privacy Register allow for 8 different duty cycles of 10%, 20%, 30%, 40%, 50%, 60%, 70%, and 80%. See Table 14 for Privacy Register bit settings. Figure 36 details the timing for the privacy-indicate mode on ILED1 or ILED2.

Figure 36. Privacy Indicate Timing

7.4.6 GPIO1 Mode

With bit [0] of the GPIO Register set to 1, the TX1/TORCH/GPIO1 pin is configured as a logic I/O. In this mode the TX1/TORCH/GPIO1 pin is readable and writable as a logic input/output via bits [2:1] of the GPIO Register. See Table 9.

7.4.7 TX2/INT/GPIO2

The TX2/INT/GPIO2 pin has a triple function. In TX2 mode (default) the TX2/INT/GPIO2 pin is an active high flash interrupt. With GPIO Register bit [3] = 1 the TX2/INT/GPIO2 pin is configured as general purpose logic I/O. With GPIO Register bit [6] = 1, and with the TX2/INT/GPIO2 pin configured as a GPIO2 output, the TX2/INT/GPIO2 pin is an interrupt output.

7.4.8 TX2 Mode

In TX2 mode, when Configuration Register 1, bit [6] = 0, the TX2/INT/GPIO2 pin has active low polarity. Under this condition when the LM3559 is engaged in a flash event and TX2 is pulled low, both LED1 and LED2 are forced into torch mode. In TX2 mode with Configuration Register 1, bit [6] = 1 the TX2/INT/GPIO2 input has active high polarity. Under this condition when the LM3559 is engaged in a flash event and the TX2/INT/GPIO2 pin is driven high, both LED1 and LED2 are forced into torch mode. During a flash interrupt event if the TX2/INT/GPIO2 input is disengaged the LED current returns to the previous flash current level. During a flash event, if TX2 is active, the LED current sources still turn off after the flash timeout. Figure 25 details the functionality of the TX2 Interrupt.

7.4.9 GPIO2 Mode

With Bit [3] of the GPIO Register set to 1, the TX2/INT/GPIO2 pin is configured as a logic I/O. In this mode the TX2/INT/GPIO2 pin is readable and writeable as a logic input/output via bits [5:4] of the GPIO Register. See Table 9.

7.4.10 Interrupt Output (INT Mode)

The TX2/INT/GPIO2 pin can be reconfigured as an active low interrupt output by setting bit [6] in the GPIO Register to 1 and configuring TX2/INT/GPIO2 as a GPIO2 output. In this mode, TX2/INT/GPIO2 pulls low when any of these conditions exist.

1. The LM3559 is configured for NTC mode (Configuration Register 1 bit [4] = 1) and the voltage at LEDI/NTC has fallen below V_TRIP (1 V typical).
2. The LM3559 is configured for V_IN monitor mode (VIN Monitor Register bit [0] = 1) and V_IN is below the programmed VIN Monitor Threshold.
3. The LM3559 is configured for V_IN flash monitor mode (VIN Monitor Register bit [3] = 1) and V_IN falls below the programmed V_IN flash monitor threshold. Figure 37 shows the functionality of the TX2/INT/GPIO2 input.

Once INT is pulled low due to any of the above conditions having been met, INT only goes back high again if any of the conditions are no longer true and the Flags Register is read.

Figure 37. TX2 as an Interrupt Output (During an NTC Event)

7.4.11 NTC Mode

Writing a 1 to the Configuration Register 1 bit [4] configures the LEDI/NTC pin for NTC mode. In this mode the indicator current source is disabled and LEDI/NTC becomes the positive input to the NTC comparator. NTC mode operates as a LED current interrupt that is triggered when the voltage at LEDI/NTC goes below 1 V.

Two actions can be taken when the NTC comparator is tripped. With Configuration Register 2 bit [1] set to 0 the NTC interrupt forces the LED current from flash mode into torch mode. With Configuration Register 2 bit [1] set to 1 the NTC interrupt forces the LED current into shutdown.

Whether in NTC force torch or NTC shutdown, in order to re-enter flash mode or torch mode after an NTC event, two things must occur. First, the NTC input must be above the 1-V threshold. Secondly, the Flags Register must be read.

To avoid noise from falsely triggering the NTC comparator, this mode incorporates a 250-µs deglitch timer. With NTC mode active, V_LEDI/NTC must go below the trip point (V_TRIP), and remain below it, for 250 µs before the LEDs are forced into torch mode (or shut down) and the NTC flag is written.

7.4.12 Alternate External Torch (AET Mode)

Configuration Register 2 bit [2] programs the LM3559 for AET mode. With this bit set to 0 (default) TX1/TORCH is a flash current interrupt that forces torch mode only during a flash event. For example, if TX1/TORCH goes high while the LED current is in flash mode, the LEDs are forced into torch mode only for the duration of the timeout counter. At the end of the timeout counter the LEDs turn off.

With the Configuration Register 2 bit [2] set to 1 the LM3559 is configured for AET mode and the operation of TX1/TORCH becomes dependent on its occurrence relative to the STROBE input. In this mode, if TX1/TORCH goes high first, then STROBE goes high next, the LEDs are forced into Torch mode with no timeout. In this mode, if TX1/TORCH goes high after STROBE has gone high, then the TX1/TORCH pin operates as a normal LED current interrupt and the LEDs turn off at the end of the timeout duration (see Figure 38.

Figure 38. AET Mode Timing

7.4.13 Automatic Conversion Mode

With the ADC enabled, a conversion is performed each time a flash pulse is started. When a flash pulse is started bit [6] of the VLED Monitor Register (end-of-conversion bit) is automatically written with a 0. At the end of the conversion, bit [6] goes high signaling that the V_LED data is valid. A read back of the VLED Monitor Register clears the EOC bit. Figure 32 shows the V_LED monitor automatic conversion.

7.4.14 Manual Conversion Mode

The V_LED monitor can be set up for manual conversion mode by setting bit [4] of the VLED Monitor Register to 1. When this bit is set high the EOC bit (bit [6]) goes low, and a conversion is performed. When the conversion is complete, the EOC bit goes high again. Subsequent conversions are performed in manual mode by reading back the VLED Monitor Register, which resets the EOC bit and starts another conversion (see Figure 33).

7.5.1 I²C-Compatible Interface

7.5.1.1 START and STOP Conditions

The LM3559 is controlled via an I²C-compatible interface. START and STOP conditions classify the beginning and end of the I²C session. A START condition is defined as SDA transitioning from HIGH to LOW while SCL is HIGH. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates the START and STOP conditions.

Figure 39. START and STOP Sequences

The I²C bus is considered busy after a START condition and free after a STOP condition. During data transmission the I²C master can generate repeated START conditions. A START and a repeated START condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 40 shows the SDA and SCL signal timing for the I²C-Compatible bus. See the Electrical Characteristics for timing values.

Figure 40. I²C-Compatible Timing

7.5.1.2 I²C-Compatible Chip Address

The device address for the LM3559 is 1010011 (0xA7 for read and 0xA6 for write). After the START condition, the I²C master sends the 7-bit address followed by an eighth read or write bit (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address selects the register address to which the data will be written. The third byte contains the data for the selected register.

Figure 41. Device Address

Table 1. LM3559 Internal Registers

7.6.1 Enable Register

Bits [1:0] of the Enable Register controls the ON/OFF state of torch mode, flash mode, and privacy-indicate mode. Bits [4:3] turn on/off the main current sources (LED1 and LED2). Bit [5] sets the level or edge control for the STROBE input. Bits 7 and 6 control the indicator current source (see Table 2).

7.6.2 Torch Brightness Register

Bits [2:0] of the Torch Brightness Register set the Torch current for LED1. Bits [5:3] set the torch current for LED2. (see Table 3).

7.6.3 Flash Brightness Register

Bits [3:0] of the Flash Brightness Register set the Flash current for LED1. Bits [7:4] set the Flash current for LED2. (see Table 4).

7.6.4 Flash Duration Register

Bits [4:0] of the Flash Duration Register set the flash timeout duration. Bits [6:5] set the switch current limit (see Table 5).

7.6.5 Flags Register

The Flags Register holds the flag bits indicating flash timeout, thermal shutdown, LED fault (open or short), TX interrupts (TX1 and TX2), LED thermal fault (NTC), V_IN monitor trip, and V_IN flash monitor trip. All flags are cleared on read back of the Flags Register (see Table 6).

7.6.6 Configuration Register 1

Configuration Register 1 holds the STROBE input enable bit, the STROBE polarity bit, the NTC enable bit, the polarity selection bits for TX1 and TX2, and the hardware-torch enable bit (see Table 7).

7.6.7 Configuration Register 2

Configuration Register 2 holds the TX2 shutdown select bit, the NTC shutdown select bit, the AET-mode enable bit, and the V_IN monitor shutdown bit (see Table 8).

7.6.8 GPIO Register

The GPIO Register contains the control bits which change the state of the TX1/TORCH/GPIO1 pin and the TX2/INT/GPIO2 pins to general purpose I/Os (GPIOs). Additionally, bit 6 of the GPIO Register contains the interrupt configuration bit. Table 9 describes the bit description and functionality of the GPIO register. To configure the TX1 or TX2 pins as GPIO outputs an initial double write is required to register 0x20. For example, to configure TX2 to output a logic high, an initial write of 0xB8 would need to occur twice to force GPIO2 low. Subsequent writes to GPIO2 after the initial setup only requires a single write. To read back the GPIO inputs, a write, then a read, of register 0x20 must occur each time the data is read. For example, if GPIO2 is set up as a GPIO input and the GPIO2 input has then changed state, first a write to 0x20 must occur, then the readback of register 0x20 that follows shows the updated data. When configuring TX2 as an interrupt output, the TX2/GPIO2/INT pin must first be configured as a GPIO output (double write). For example, to configure TX2/GPIO2/INT for INT mode, a write of 0xF8 to register 0x20 must be done twice.

7.6.9 Last Flash Register

The Last Flash Register is a read-only register loaded with the flash code corresponding to the flash level that the device was at if any of the following events happens:

1. Voltage at LEDI/NTC falling below V_TRIP with the device in NTC mode (Configuration Register 1 bit [4] = 1)
2. Input voltage falling below the programmed V_IN monitor threshold with device in V_IN monitor mode (VIN Monitor Register bit [0] = 1)
3. Input voltage falling below the programmed V_IN flash monitor threshold with the device in V_IN flash monitor mode (VIN Monitor Register bit [3] = 1).

The Last Flash Register is updated at the same time that the corresponding flag bit is written to the Flags Register. This results in a delay of 250 µs from when V_LEDI/NTC (NTC mode) crosses V_TRIP, or V_IN (V_IN monitor enabled) crosses the V_{IN_TH}. During V_IN flash monitor there is a 8-µs deglitch time so the V_IN flash monitor flag is written (and the Last Flash Register is updated) 8 µs after V_IN falls below V_{IN_FLASH}.

7.6.10 VLED Monitor Register

The VLED Monitor Register controls the internal 4-bit analog to digital converter. Bits [3:0] of this register contain the 4-bit data of the LED voltage. This data is the digitized voltage of the highest of either VLED1 to GND or VLED2 to GND. Bit [4] is the manual mode enable which provides for a manual conversion of the ADC. In manual mode the automatic conversion is still performed. In automatic conversion mode a conversion is performed each time a flash pulse is initiated. Bit [5] is the ADC shutdown bit. Bit [6] signals the end of conversion. This is a read-only bit that goes high when a conversion is complete and data is ready. A read of the VLED Monitor Register clears the EOC bit (see Table 11).

7.6.11 ADC Delay Register

The ADC Delay Register programs the delay from when the EOC bit goes low to when a conversion is initiated. This delay applies to both manual mode and automatic mode. Bit 5 is the no-delay bit and can set the delay to effectively 0 (see Table 12, Figure 32, and Figure 33).

7.6.12 Input Voltage Monitor Register

The VIN Monitor Register contains the enable bit for the V_IN monitor, the threshold select for the V_IN monitor, the enable bit for the V_IN flash monitor, and the threshold select for the V_IN flash monitor (see Table 13).

7.6.13 Privacy Register

The Privacy Register contains the bits to control which current source is used for the privacy indicator (LED1 or LED2 or both), whether the privacy indicator turns off or remains on after the flash pulse terminates, and the duty cycle settings (between 10% and 80%) for setting the privacy LED current (see Table 14).

7.6.14 Privacy PWM Period Register

The Privacy PWM Register contains the bits to control the PWM period for the privacy indicate mode (see Table 15).

7.6.15 Indicator Register

The Message Indicator Register contain the bits which control the following:

1. Indicator current level
2. Pulse width
3. Ramp times for turnon and turnoff of the indicator current source (see Figure 42 for the message indicator timing diagram).

7.6.16 Indicator Blinking Register

The Indicator Blinking Register contain the bits which control the following:

1. Number of periods (t_PERIOD = t_RAMP × 2 + t_PULSE × 2)
2. Active Time (t_ACTIVE = t_PERIOD × PERIOD# )
3. Blank Time (t_BLANK = t_ACTIVE × BLANK#)
   • (see Figure 42)

Figure 42. Message Indicator Timing Diagram