10.1 Layout Guidelines

PC board layout is critical to successfully designing a DC-DC converter into a product. As much as a 10-dB improvement in RX noise floor can be achieved by carefully following recommended layout practices. A properly planned board layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also addressing manufacturing issues that can have adverse impacts on board quality and final product yield.

Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC converter IC, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or degraded performance of the converter.

10.2 Layout Examples

Top Layer (Figure 28)

1. Create a PGND island as shown. PGND pads of C2 (CIN) and C3 (COUT) must be isolated from each other. This PGND island will connect to the dedicated system ground with many vias.
2. Each SW (C3) and (D4) bump will have a via in pad and an additional via next to it, to drop down the SW trace to layer 3.
3. SGND bump (C2) and GND (D1) will have a via in pad, and directly connecting it to the system ground.
4. FB (C2) should connect directly to the VOUT bump (D1).
5. Have PVIN vias next to optional ferrite bead.

Layer 2 (Figure 29)

6. Digital logic signals may be routed on this layer.
7. PVIN for the LM3279 can be routed on this layer.
8. VCC2 can be routed on this layer.

Layer 3 (Figure 30)

9. Each SW trace is routed on this layer. The width of each trace should be 15 mils (0.381 mm) for current capabilities. Have two vias bring each SW trace up to the inductor pads.

Layer 4 (Figure 31)

10. Connect the PGND, SGND, and high Frequency vias from the top layer on this layer.

Figure 28. Top Layer

Figure 29. Board Layer 2 - Logic And PVIN Routing

Figure 30. Board Layer 3 - SW Routing

Figure 31. Board Layer 4 - System GND Plane

10.2.1 LM3279 RF Evaluation Board

Figure 32. Simplified LM3279 RF Evaluation Board Schematic

1. Input Capacitor C2 should be placed closer to LM3279 than C1.
2. Optional to add a 100 nF (C1) on input of LM3279 for high frequency filtering.
3. Bulk Output Capacitor C3 should be placed closer to LM3279 than C4.
4. Optional to add a 100 nF (C4) on output of LM3279 for high frequency filtering.
5. Connect both GND terminals of C1 and C4 directly to System RF GND layer of phone board.
6. Connect bumps SGND (C3) and GND (D1) directly to System GND.
7. TI has seen improvement in high frequency filtering for small bypass caps (C1 and C4) when they are connected to System GND instead of same ground as PGND. These capacitors should be 0201 (0603 metric) case size for minimum footprint and best high frequency characteristics.

10.2.2 Component Placement

Figure 33. LM3279 Recommended Parts Placement (Top View)

10.3 DSBGA Package Assembly And Use

Use of the DSBGA package requires specialized board layout, precision mounting, and careful re-flow techniques, as detailed in Texas Instruments Application Note 1112 (SNVA009). Refer to the section Surface Mount Technology (SMD) Assembly Considerations. For best results in assembly, alignment ordinals on the PC board should be used to facilitate placement of the device. The pad style used with DSBGA package must be the NSMD (non-solder mask defined) type. This means that the solder-mask opening is larger than the pad size. This prevents a lip that otherwise forms if the solder-mask and pad overlap from holding the device off the surface of the board and interfering with mounting. See SNVA009 for specific instructions how to do this.

The 16-bump package used for the LM3279 has 300 micron solder balls and requires 10.82 mil pads for mounting on the circuit board. The trace to each pad should enter the pad with a 90° entry angle to prevent debris from being caught in deep corners. Initially, the trace to each pad should be 9 mil wide, for a section approximately 9 mil long, as a thermal relief. Then each trance should neck up or down to its optimal width. The important criterion is symmetry. This ensures the solder bumps on the LM3279 re-flow evenly and that the device solders level to the board. In particular, special attention must be paid to the pads for bumps B4 and D4. Because PVIN and PGND are typically connected to large copper planes, inadequate thermal relief can result in late or inadequate re-flow of these bumps.

The DSBGA package is optimized for the smallest possible size in applications with red or infrared opaque cases. Because the DSBGA package lacks the plastic encapsulation characteristic of larger devices, it is vulnerable to light. Backside metallization and/or epoxy coating, along with front-side shading by the printed circuit board, reduce this sensitivity. However, the package has exposed die edges. In particular, DSBGA devices are sensitive to light (in the red and infrared range) shining on the package's exposed die edges.

10.4 Manufacturing Considerations

The LM3279 package employs a 16-bump (4x4) array of 300 micron solder balls, with a 0.5-mm pad pitch. A few simple design rules will go a long way to ensuring a good layout.

• Pad size should be 0.265 ± 0.02 mm. Solder mask opening should be 0.375 ± 0.02 mm.
• As a thermal relief, connect to each pad with 9.5 mil wide, 5 mil long traces and incrementally increase each trace to its optimal width. Symmetry is important to ensure the solder bumps re-flow evenly. Refer to TI Application Note AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).