ZHCSSO2 July   2023 IWRL1432

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 功能方框图
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configurations and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
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  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
      1. 8.5.1 Power Optimized 3.3V I/O Topology
      2. 8.5.2 BOM Optimized 3.3V I/O Topology
      3. 8.5.3 Power Optimized 1.8V I/O Topology
      4. 8.5.4 BOM Optimized 1.8V I/O Topology
      5. 8.5.5 System Topologies
        1. 8.5.5.1 Power Topologies
          1. 8.5.5.1.1 BOM Optimized Mode
          2. 8.5.5.1.2 Power Optimized Mode
      6. 8.5.6 Noise and Ripple Specifications
    6. 8.6  Power Save Modes
      1. 8.6.1 Typical Power Consumption Numbers
    7. 8.7  Peak Current Requirement per Voltage Rail
    8. 8.8  RF Specification
    9. 8.9  Supported DFE Features
    10. 8.10 CPU Specifications
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing and Reset Timing
      2. 8.12.2  Synchronized Frame Triggering
      3. 8.12.3  Input Clocks and Oscillators
        1. 8.12.3.1 Clock Specifications
      4. 8.12.4  MultiChannel buffered / Standard Serial Peripheral Interface (McSPI)
        1. 8.12.4.1 McSPI Features
        2. 8.12.4.2 SPI Timing Conditions
        3. 8.12.4.3 SPI—Controller Mode
          1. 8.12.4.3.1 Timing and Switching Requirements for SPI - Controller Mode
          2. 8.12.4.3.2 Timing and Switching Characteristics for SPI Output Timings—Controller Mode
        4. 8.12.4.4 SPI—Peripheral Mode
          1. 8.12.4.4.1 Timing and Switching Requirements for SPI - Peripheral Mode
          2. 8.12.4.4.2 Timing and Switching Characteristics for SPI Output Timings—Secondary Mode
      5. 8.12.5  RDIF Interface Configuration
        1. 8.12.5.1 RDIF Interface Timings
        2. 8.12.5.2 RDIF Data Format
      6. 8.12.6  General-Purpose Input/Output
        1. 8.12.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.12.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 8.12.8  Serial Communication Interface (SCI)
        1. 8.12.8.1 SCI Timing Requirements
      9. 8.12.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.12.9.1 I2C Timing Requirements
      10. 8.12.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.12.10.1 QSPI Timing Conditions
        2. 8.12.10.2 Timing Requirements for QSPI Input (Read) Timings
        3. 8.12.10.3 QSPI Switching Characteristics
      11. 8.12.11 JTAG Interface
        1. 8.12.11.1 JTAG Timing Conditions
        2. 8.12.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.12.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 功能方框图
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
      2. 9.3.2 Clock Subsystem
      3. 9.3.3 Transmit Subsystem
      4. 9.3.4 Receive Subsystem
      5. 9.3.5 Processor Subsystem
      6. 9.3.6 Host Interface
      7. 9.3.7 Main Subsystem Cortex-M4F
      8. 9.3.8 Hardware Accelerator (HWA1.2) Features
        1. 9.3.8.1 Hardware Accelerator Feature Differences Between HWA1.1 and HWA1.2
    4. 9.4 Other Subsystems
      1. 9.4.1 GPADC Channels (Service) for User Application
      2. 9.4.2 GPADC Parameters
    5. 9.5 Memory Partitioning Options
    6. 9.6 Boot Modes
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

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8.12.3.1 Clock Specifications

The IWRL1432 requires external clock source (that is, a 40-MHz crystal or external oscillator to CLKP) for initial boot and as a reference for an internal APLL hosted in the device. An external crystal connected to the device pins Figure 8-8 shows the crystal implementation.

GUID-EDE3039E-2AF2-4B30-B258-B2D36CF1C9A4-low.gifFigure 8-8 Crystal Implementation
Note:

The load capacitors, Cf1 and Cf2 in Figure 8-8, should be chosen such that Equation 1 is satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator CLKP and CLKM pins.

Equation 1. GUID-ABEB21DF-C4ED-46A1-8A95-1E534ADF5429-low.gif

Table 8-13 lists the electrical characteristics of the clock crystal.

Table 8-13 Crystal Electrical Characteristics (Oscillator Mode)
NAMEDESCRIPTIONMINTYPMAXUNIT
fPParallel resonance crystal frequency40MHz
CLCrystal load capacitance5812pF
ESRCrystal ESR50Ω
Temperature rangeExpected temperature range of operation–40105°C
Frequency toleranceCrystal frequency tolerance(1)(2)(3)–200200ppm
Drive level50200µW
(1) The crystal manufacturer's specification must satisfy this requirement.
(2) Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.
(3) Crystal tolerance affects radar sensor accuracy.

In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only; CLKM is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally. Table 8-14 lists the electrical characteristics of the external clock signal.

Table 8-14 External Clock Mode Specifications
PARAMETERSPECIFICATIONUNIT
MINTYPMAX
Input Clock:
External AC-coupled sine wave or DC-coupled square wave Phase Noise referred to 40 MHz		Frequency40MHz
AC-Amplitude7001200mV (pp)
DC-Vil0.000.20ns
DC-Vih1.61.95ns
Phase Noise at 1 kHz–132dBc/Hz
Phase Noise at 10 kHz–143dBc/Hz
Phase Noise at 100 kHz–152dBc/Hz
Phase Noise at 1 MHz–153dBc/Hz
Duty Cycle3565%
Frequency Tolerance-200200ppm