ZHCSEN6D October 2014 – February 2022 DS90UH948-Q1
PRODUCTION DATA
This device features a standalone PLL to clean the I2S data jitter, supporting high-end car audio systems. If I2S_CLK frequency is less than 1MHz, this feature must be disabled through register 0x2B[7]. See the GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF.html section.