ZHCSEN6D October 2014 – February 2022 DS90UH948-Q1
PRODUCTION DATA
The deserializer provides an optional CLK[2:1]± output when the input clock (serial stream) has been lost. This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable). See GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF.html#GUID-60BE0D45-4ECE-419B-8DBC-A833CCA113EF.