ZHCSIG1D 数据表 | 德州仪器 TI.com.cn

ZHCSIG1D August 2016 – September 2023 DS90UB960-Q1

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- MPQF141C

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7.6.2.1 PATGEN_And_CSI-2 Registers

Table 7-189 lists the memory-mapped registers for the PATGEN_And_CSI-2 registers. All register offset addresses not listed in Table 7-189 should be considered as reserved locations and the register contents should not be modified.

Table 7-189 PATGEN_AND_CSI-2 Registers

Address	Acronym	Register Name	Section
0x1	PGEN_CTL	PGEN_CTL	Go
0x2	PGEN_CFG	PGEN_CFG	Go
0x3	PGEN_CSI_DI	PGEN_CSI_DI	Go
0x4	PGEN_LINE_SIZE1	PGEN_LINE_SIZE1	Go
0x5	PGEN_LINE_SIZE0	PGEN_LINE_SIZE0	Go
0x6	PGEN_BAR_SIZE1	PGEN_BAR_SIZE1	Go
0x7	PGEN_BAR_SIZE0	PGEN_BAR_SIZE0	Go
0x8	PGEN_ACT_LPF1	PGEN_ACT_LPF1	Go
0x9	PGEN_ACT_LPF0	PGEN_ACT_LPF0	Go
0xA	PGEN_TOT_LPF1	PGEN_TOT_LPF1	Go
0xB	PGEN_TOT_LPF0	PGEN_TOT_LPF0	Go
0xC	PGEN_LINE_PD1	PGEN_LINE_PD1	Go
0xD	PGEN_LINE_PD0	PGEN_LINE_PD0	Go
0xE	PGEN_VBP	PGEN_VBP	Go
0xF	PGEN_VFP	PGEN_VFP	Go
0x10	PGEN_COLOR0	PGEN_COLOR0	Go
0x11	PGEN_COLOR1	PGEN_COLOR1	Go
0x12	PGEN_COLOR2	PGEN_COLOR2	Go
0x13	PGEN_COLOR3	PGEN_COLOR3	Go
0x14	PGEN_COLOR4	PGEN_COLOR4	Go
0x15	PGEN_COLOR5	PGEN_COLOR5	Go
0x16	PGEN_COLOR6	PGEN_COLOR6	Go
0x17	PGEN_COLOR7	PGEN_COLOR7	Go
0x18	PGEN_COLOR8	PGEN_COLOR8	Go
0x19	PGEN_COLOR9	PGEN_COLOR9	Go
0x1A	PGEN_COLOR10	PGEN_COLOR10	Go
0x1B	PGEN_COLOR11	PGEN_COLOR11	Go
0x1C	PGEN_COLOR12	PGEN_COLOR12	Go
0x1D	PGEN_COLOR13	PGEN_COLOR13	Go
0x1E	PGEN_COLOR14	PGEN_COLOR14	Go
0x40	CSI0_TCK_PREP	CSI0_TCK_PREP	Go
0x41	CSI0_TCK_ZERO	CSI0_TCK_ZERO	Go
0x42	CSI0_TCK_TRAIL	CSI0_TCK_TRAIL	Go
0x43	CSI0_TCK_POST	CSI0_TCK_POST	Go
0x44	CSI0_THS_PREP	CSI0_THS_PREP	Go
0x45	CSI0_THS_ZERO	CSI0_THS_ZERO	Go
0x46	CSI0_THS_TRAIL	CSI0_THS_TRAIL	Go
0x47	CSI0_THS_EXIT	CSI0_THS_EXIT	Go
0x48	CSI0_TPLX	CSI0_TPLX	Go
0x60	CSI1_TCK_PREP	CSI1_TCK_PREP	Go
0x61	CSI1_TCK_ZERO	CSI1_TCK_ZERO	Go
0x62	CSI1_TCK_TRAIL	CSI1_TCK_TRAIL	Go
0x63	CSI1_TCK_POST	CSI1_TCK_POST	Go
0x64	CSI1_THS_PREP	CSI1_THS_PREP	Go
0x65	CSI1_THS_ZERO	CSI1_THS_ZERO	Go
0x66	CSI1_THS_TRAIL	CSI1_THS_TRAIL	Go
0x67	CSI1_THS_EXIT	CSI1_THS_EXIT	Go
0x68	CSI1_TPLX	CSI1_TPLX	Go

Complex bit access types are encoded to fit into small table cells. Table 7-190 shows the codes that are used for access types in this section.

Table 7-190 PATGEN_And_CSI-2 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

6.2.1.1 PGEN_CTL Register (Address = 0x1) [Reset = 0x00]

PGEN_CTL is shown in Table 7-191.

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Table 7-191 PGEN_CTL Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R	0x0	Reserved
0	PGEN_ENABLE	R/W	0x0	Pattern Generator Enable 1: Enable Pattern Generator 0: Disable Pattern Generator

6.2.1.2 PGEN_CFG Register (Address = 0x2) [Reset = 0x33]

PGEN_CFG is shown in Table 7-192.

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Table 7-192 PGEN_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PGEN_FIXED_EN	R/W	0x0	Fixed Pattern Enable Setting this bit enables Fixed Color Patterns. 0: Send Color Bar Pattern 1: Send Fixed Color Pattern
6	RESERVED	R	0x0	Reserved
5:4	NUM_CBARS	R/W	0x3	Number of Color Bars 00: 1 Color Bar 01: 2 Color Bars 10: 4 Color Bars 11: 8 Color Bars
3:0	BLOCK_SIZE	R/W	0x3	Block Size. For Fixed Color Patterns, this field controls the size of the fixed color field in bytes. Allowed values are 1 to 15.

6.2.1.3 PGEN_CSI_DI Register (Address = 0x3) [Reset = 0x24]

PGEN_CSI_DI is shown in Table 7-193.

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Table 7-193 PGEN_CSI_DI Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	PGEN_CSI_VC	R/W	0x0	CSI-2 Virtual Channel Identifier This field controls the value sent in the CSI-2 packet for the Virtual Channel Identifier
5:0	PGEN_CSI_DT	R/W	0x24	CSI-2 Data Type This field controls the value sent in the CSI-2 packet for the Data Type. The default value (0x24) indicates RGB888.

6.2.1.4 PGEN_LINE_SIZE1 Register (Address = 0x4) [Reset = 0x07]

PGEN_LINE_SIZE1 is shown in Table 7-194.

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Table 7-194 PGEN_LINE_SIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_LINE_SIZE[15:8]	R/W	0x7	Most significant byte of the Pattern Generator line size. This is the active line length in bytes. Default setting is for 1920 bytes for a 640 pixel line width.

6.2.1.5 PGEN_LINE_SIZE0 Register (Address = 0x5) [Reset = 0x80]

PGEN_LINE_SIZE0 is shown in Table 7-195.

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Table 7-195 PGEN_LINE_SIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_LINE_SIZE[7:0]	R/W	0x80	Least significant byte of the Pattern Generator line size. This is the active line length in bytes. Default setting is for 1920 bytes for a 640 pixel line width.

6.2.1.6 PGEN_BAR_SIZE1 Register (Address = 0x6) [Reset = 0x00]

PGEN_BAR_SIZE1 is shown in Table 7-196.

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Table 7-196 PGEN_BAR_SIZE1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_BAR_SIZE[15:8]	R/W	0x0	Most significant byte of the Pattern Generator color bar size. This is the active length in bytes for the color bars. This value is used for all except the last color bar. The last color bar is determined by the remaining bytes as defined by the PGEN_LINE_SIZE value.

6.2.1.7 PGEN_BAR_SIZE0 Register (Address = 0x7) [Reset = 0xF0]

PGEN_BAR_SIZE0 is shown in Table 7-197.

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Table 7-197 PGEN_BAR_SIZE0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_BAR_SIZE[7:0]	R/W	0xF0	Least significant byte of the Pattern Generator color bar size. This is the active length in bytes for the color bars. This value is used for all except the last color bar. The last color bar is determined by the remaining bytes as defined by the PGEN_LINE_SIZE value.

6.2.1.8 PGEN_ACT_LPF1 Register (Address = 0x8) [Reset = 0x01]

PGEN_ACT_LPF1 is shown in Table 7-198.

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Table 7-198 PGEN_ACT_LPF1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_ACT_LPF[15:8]	R/W	0x1	Active Lines Per Frame Most significant byte of the number of active lines per frame. Default setting is for 480 active lines per frame.

6.2.1.9 PGEN_ACT_LPF0 Register (Address = 0x9) [Reset = 0xE0]

PGEN_ACT_LPF0 is shown in Table 7-199.

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Table 7-199 PGEN_ACT_LPF0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_ACT_LPF[7:0]	R/W	0xE0	Active Lines Per Frame Least significant byte of the number of active lines per frame. Default setting is for 480 active lines per frame.

6.2.1.10 PGEN_TOT_LPF1 Register (Address = 0xA) [Reset = 0x02]

PGEN_TOT_LPF1 is shown in Table 7-200.

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Table 7-200 PGEN_TOT_LPF1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_TOT_LPF[15:8]	R/W	0x2	Total Lines Per Frame Most significant byte of the number of total lines per frame including vertical blanking

6.2.1.11 PGEN_TOT_LPF0 Register (Address = 0xB) [Reset = 0x0D]

PGEN_TOT_LPF0 is shown in Table 7-201.

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Table 7-201 PGEN_TOT_LPF0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_TOT_LPF[7:0]	R/W	0xD	Total Lines Per Frame Least significant byte of the number of total lines per frame including vertical blanking

6.2.1.12 PGEN_LINE_PD1 Register (Address = 0xC) [Reset = 0x0C]

PGEN_LINE_PD1 is shown in Table 7-202.

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Table 7-202 PGEN_LINE_PD1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_LINE_PD[15:8]	R/W	0xC	Line Period Most significant byte of the line period. In 800 Mbps and 1.6 Gbps CSI-2 modes, units are 10 ns and the default setting for the line period registers sets a line period of 31.75 microseconds. In 1.2 Gbps CSI-2 mode, units are 13.33 ns and the default setting for the line period registers sets a line period of 42.33 microseconds. In 400 Mbps CSI-2 mode, units are 20 ns and the default setting for the line period registers sets a line period of 63.5 microseconds.

6.2.1.13 PGEN_LINE_PD0 Register (Address = 0xD) [Reset = 0x67]

PGEN_LINE_PD0 is shown in Table 7-203.

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Table 7-203 PGEN_LINE_PD0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_LINE_PD[7:0]	R/W	0x67	Line Period Least significant byte of the line period. In 800 Mbps and 1.6 Gbps CSI-2 modes, units are 10 ns and the default setting for the line period registers sets a line period of 31.75 microseconds. In 1.2 Gbps CSI-2 mode, units are 13.33 ns and the default setting for the line period registers sets a line period of 42.33 microseconds. In 400 Mbps CSI-2 mode, units are 20 ns and the default setting for the line period registers sets a line period of 63.5 microseconds.

6.2.1.14 PGEN_VBP Register (Address = 0xE) [Reset = 0x21]

PGEN_VBP is shown in Table 7-204.

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Table 7-204 PGEN_VBP Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_VBP	R/W	0x21	Vertical Back Porch This value provides the vertical back porch portion of the vertical blanking interval. This value provides the number of blank lines between the FrameStart packet and the first video data packet.

6.2.1.15 PGEN_VFP Register (Address = 0xF) [Reset = 0x0A]

PGEN_VFP is shown in Table 7-205.

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Table 7-205 PGEN_VFP Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_VFP	R/W	0xA	Vertical Front Porch This value provides the vertical front porch portion of the vertical blanking interval. This value provides the number of blank lines between the last video line and the FrameEnd packet.

6.2.1.16 PGEN_COLOR0 Register (Address = 0x10) [Reset = 0xAA]

PGEN_COLOR0 is shown in Table 7-206.

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Table 7-206 PGEN_COLOR0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR0	R/W	0xAA	Pattern Generator Color 0 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 0. For Fixed Color Patterns, this register controls the first byte of the fixed color pattern.

6.2.1.17 PGEN_COLOR1 Register (Address = 0x11) [Reset = 0x33]

PGEN_COLOR1 is shown in Table 7-207.

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Table 7-207 PGEN_COLOR1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR1	R/W	0x33	Pattern Generator Color 1 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 1. For Fixed Color Patterns, this register controls the second byte of the fixed color pattern.

6.2.1.18 PGEN_COLOR2 Register (Address = 0x12) [Reset = 0xF0]

PGEN_COLOR2 is shown in Table 7-208.

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Table 7-208 PGEN_COLOR2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR2	R/W	0xF0	Pattern Generator Color 2 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 2. For Fixed Color Patterns, this register controls the third byte of the fixed color pattern.

6.2.1.19 PGEN_COLOR3 Register (Address = 0x13) [Reset = 0x7F]

PGEN_COLOR3 is shown in Table 7-209.

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Table 7-209 PGEN_COLOR3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR3	R/W	0x7F	Pattern Generator Color 3 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 3. For Fixed Color Patterns, this register controls the fourth byte of the fixed color pattern.

6.2.1.20 PGEN_COLOR4 Register (Address = 0x14) [Reset = 0x55]

PGEN_COLOR4 is shown in Table 7-210.

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Table 7-210 PGEN_COLOR4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR4	R/W	0x55	Pattern Generator Color 4 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 4. For Fixed Color Patterns, this register controls the fifth byte of the fixed color pattern.

6.2.1.21 PGEN_COLOR5 Register (Address = 0x15) [Reset = 0xCC]

PGEN_COLOR5 is shown in Table 7-211.

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Table 7-211 PGEN_COLOR5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR5	R/W	0xCC	Pattern Generator Color 5 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 5. For Fixed Color Patterns, this register controls the sixth byte of the fixed color pattern.

6.2.1.22 PGEN_COLOR6 Register (Address = 0x16) [Reset = 0x0F]

PGEN_COLOR6 is shown in Table 7-212.

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Table 7-212 PGEN_COLOR6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR6	R/W	0xF	Pattern Generator Color 6 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 6. For Fixed Color Patterns, this register controls the seventh byte of the fixed color pattern.

6.2.1.23 PGEN_COLOR7 Register (Address = 0x17) [Reset = 0x80]

PGEN_COLOR7 is shown in Table 7-213.

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Table 7-213 PGEN_COLOR7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR7	R/W	0x80	Pattern Generator Color 7 For Reference Color Bar Patterns, this register controls the byte data value sent during color bar 7. For Fixed Color Patterns, this register controls the eighth byte of the fixed color pattern.

6.2.1.24 PGEN_COLOR8 Register (Address = 0x18) [Reset = 0x00]

PGEN_COLOR8 is shown in Table 7-214.

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Table 7-214 PGEN_COLOR8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR8	R/W	0x0	Pattern Generator Color 8 For Fixed Color Patterns, this register controls the ninth byte of the fixed color pattern.

6.2.1.25 PGEN_COLOR9 Register (Address = 0x19) [Reset = 0x00]

PGEN_COLOR9 is shown in Table 7-215.

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Table 7-215 PGEN_COLOR9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR9	R/W	0x0	Pattern Generator Color 9 For Fixed Color Patterns, this register controls the tenth byte of the fixed color pattern.

6.2.1.26 PGEN_COLOR10 Register (Address = 0x1A) [Reset = 0x00]

PGEN_COLOR10 is shown in Table 7-216.

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Table 7-216 PGEN_COLOR10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR10	R/W	0x0	Pattern Generator Color 10 For Fixed Color Patterns, this register controls the eleventh byte of the fixed color pattern.

6.2.1.27 PGEN_COLOR11 Register (Address = 0x1B) [Reset = 0x00]

PGEN_COLOR11 is shown in Table 7-217.

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Table 7-217 PGEN_COLOR11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR11	R/W	0x0	Pattern Generator Color 11 For Fixed Color Patterns, this register controls the twelfth byte of the fixed color pattern.

6.2.1.28 PGEN_COLOR12 Register (Address = 0x1C) [Reset = 0x00]

PGEN_COLOR12 is shown in Table 7-218.

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Table 7-218 PGEN_COLOR12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR12	R/W	0x0	Pattern Generator Color 12 For Fixed Color Patterns, this register controls the thirteenth byte of the fixed color pattern.

6.2.1.29 PGEN_COLOR13 Register (Address = 0x1D) [Reset = 0x00]

PGEN_COLOR13 is shown in Table 7-219.

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Table 7-219 PGEN_COLOR13 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR13	R/W	0x0	Pattern Generator Color 13 For Fixed Color Patterns, this register controls the fourteenth byte of the fixed color pattern.

6.2.1.30 PGEN_COLOR14 Register (Address = 0x1E) [Reset = 0x00]

PGEN_COLOR14 is shown in Table 7-220.

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Table 7-220 PGEN_COLOR14 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_COLOR14	R/W	0x0	Pattern Generator Color 14 For Fixed Color Patterns, this register controls the fifteenth byte of the fixed color pattern.

6.2.1.31 CSI0_TCK_PREP Register (Address = 0x40) [Reset = 0x05]

CSI0_TCK_PREP is shown in Table 7-221.

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Table 7-221 CSI0_TCK_PREP Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TCK_PREP_OV	R/W	0x0	Override CSI-2 Tck-prep parameter 0: Tck-prep is automatically determined 1: Override Tck-prep with value in bits 6:0 of this register
6:0	MR_TCK_PREP	R/W	0x5	Tck-prep value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.32 CSI0_TCK_ZERO Register (Address = 0x41) [Reset = 0x1B]

CSI0_TCK_ZERO is shown in Table 7-222.

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Table 7-222 CSI0_TCK_ZERO Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TCK_ZERO_OV	R/W	0x0	Override CSI-2 Tck-zero parameter 0: Tck-zero is automatically determined 1: Override Tck-zero with value in bits 6:0 of this register
6:0	MR_TCK_ZERO	R/W	0x1B	Tck-zero value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.33 CSI0_TCK_TRAIL Register (Address = 0x42) [Reset = 0x0B]

CSI0_TCK_TRAIL is shown in Table 7-223.

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Table 7-223 CSI0_TCK_TRAIL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TCK_TRAIL_OV	R/W	0x0	Override CSI-2 Tck-trail parameter 0: Tck-trail is automatically determined 1: Override Tck-trail with value in bits 6:0 of this register
6:0	MR_TCK_TRAIL	R/W	0xB	Tck-trail value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.34 CSI0_TCK_POST Register (Address = 0x43) [Reset = 0x0A]

CSI0_TCK_POST is shown in Table 7-224.

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Table 7-224 CSI0_TCK_POST Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TCK_POST_OV	R/W	0x0	Override CSI-2 Tck-post parameter 0: Tck-post is automatically determined 1: Override Tck-post with value in bits 6:0 of this register
6:0	MR_TCK_POST	R/W	0xA	Tck-post value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.35 CSI0_THS_PREP Register (Address = 0x44) [Reset = 0x06]

CSI0_THS_PREP is shown in Table 7-225.

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Table 7-225 CSI0_THS_PREP Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_THS_PREP_OV	R/W	0x0	Override CSI-2 Ths-prep parameter 0: Ths-prep is automatically determined 1: Override Ths-prep with value in bits 6:0 of this register
6:0	MR_THS_PREP	R/W	0x6	Ths-prep value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.36 CSI0_THS_ZERO Register (Address = 0x45) [Reset = 0x0C]

CSI0_THS_ZERO is shown in Table 7-226.

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Table 7-226 CSI0_THS_ZERO Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_THS_ZERO_OV	R/W	0x0	Override CSI-2 Ths-zero parameter 0: Ths-zero is automatically determined 1: Override Ths-zero with value in bits 6:0 of this register
6:0	MR_THS_ZERO	R/W	0xC	Ths-zero value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.37 CSI0_THS_TRAIL Register (Address = 0x46) [Reset = 0x08]

CSI0_THS_TRAIL is shown in Table 7-227.

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Table 7-227 CSI0_THS_TRAIL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_THS_TRAIL_OV	R/W	0x0	Override CSI-2 Ths-trail parameter 0: Ths-trail is automatically determined 1: Override Ths-trail with value in bits 6:0 of this register
6:0	MR_THS_TRAIL	R/W	0x8	Ths-trail value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.38 CSI0_THS_EXIT Register (Address = 0x47) [Reset = 0x0B]

CSI0_THS_EXIT is shown in Table 7-228.

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Table 7-228 CSI0_THS_EXIT Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_THS_EXIT_OV	R/W	0x0	Override CSI-2 Ths-exit parameter 0: Ths-exit is automatically determined 1: Override Ths-exit with value in bits 6:0 of this register
6:0	MR_THS_EXIT	R/W	0xB	Ths-exit value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.39 CSI0_TPLX Register (Address = 0x48) [Reset = 0x06]

CSI0_TPLX is shown in Table 7-229.

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Table 7-229 CSI0_TPLX Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TPLX_OV	R/W	0x0	Override CSI-2 Tplx parameter 0: Tplx is automatically determined 1: Override Tplx with value in bits 6:0 of this register
6:0	MR_TPLX	R/W	0x6	Tplx value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.40 CSI1_TCK_PREP Register (Address = 0x60) [Reset = 0x05]

CSI1_TCK_PREP is shown in Table 7-230.

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Table 7-230 CSI1_TCK_PREP Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TCK_PREP_OV	R/W	0x0	Override CSI-2 Tck-prep parameter 0: Tck-prep is automatically determined 1: Override Tck-prep with value in bits 6:0 of this register
6:0	MR_TCK_PREP	R/W	0x5	Tck-prep value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.41 CSI1_TCK_ZERO Register (Address = 0x61) [Reset = 0x1B]

CSI1_TCK_ZERO is shown in Table 7-231.

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Table 7-231 CSI1_TCK_ZERO Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TCK_ZERO_OV	R/W	0x0	Override CSI-2 Tck-zero parameter 0: Tck-zero is automatically determined 1: Override Tck-zero with value in bits 6:0 of this register
6:0	MR_TCK_ZERO	R/W	0x1B	Tck-zero value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.42 CSI1_TCK_TRAIL Register (Address = 0x62) [Reset = 0x0B]

CSI1_TCK_TRAIL is shown in Table 7-232.

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Table 7-232 CSI1_TCK_TRAIL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TCK_TRAIL_OV	R/W	0x0	Override CSI-2 Tck-trail parameter 0: Tck-trail is automatically determined 1: Override Tck-trail with value in bits 6:0 of this register
6:0	MR_TCK_TRAIL	R/W	0xB	Tck-trail value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.43 CSI1_TCK_POST Register (Address = 0x63) [Reset = 0x0A]

CSI1_TCK_POST is shown in Table 7-233.

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Table 7-233 CSI1_TCK_POST Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TCK_POST_OV	R/W	0x0	Override CSI-2 Tck-post parameter 0: Tck-post is automatically determined 1: Override Tck-post with value in bits 6:0 of this register
6:0	MR_TCK_POST	R/W	0xA	Tck-post value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.44 CSI1_THS_PREP Register (Address = 0x64) [Reset = 0x06]

CSI1_THS_PREP is shown in Table 7-234.

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Table 7-234 CSI1_THS_PREP Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_THS_PREP_OV	R/W	0x0	Override CSI-2 Ths-prep parameter 0: Ths-prep is automatically determined 1: Override Ths-prep with value in bits 6:0 of this register
6:0	MR_THS_PREP	R/W	0x6	Ths-prep value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.45 CSI1_THS_ZERO Register (Address = 0x65) [Reset = 0x0C]

CSI1_THS_ZERO is shown in Table 7-235.

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Table 7-235 CSI1_THS_ZERO Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_THS_ZERO_OV	R/W	0x0	Override CSI-2 Ths-zero parameter 0: Ths-zero is automatically determined 1: Override Ths-zero with value in bits 6:0 of this register
6:0	MR_THS_ZERO	R/W	0xC	Ths-zero value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.46 CSI1_THS_TRAIL Register (Address = 0x66) [Reset = 0x08]

CSI1_THS_TRAIL is shown in Table 7-236.

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Table 7-236 CSI1_THS_TRAIL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_THS_TRAIL_OV	R/W	0x0	Override CSI-2 Ths-trail parameter 0: Ths-trail is automatically determined 1: Override Ths-trail with value in bits 6:0 of this register
6:0	MR_THS_TRAIL	R/W	0x8	Ths-trail value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.47 CSI1_THS_EXIT Register (Address = 0x67) [Reset = 0x0B]

CSI1_THS_EXIT is shown in Table 7-237.

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Table 7-237 CSI1_THS_EXIT Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_THS_EXIT_OV	R/W	0x0	Override CSI-2 Ths-exit parameter 0: Ths-exit is automatically determined 1: Override Ths-exit with value in bits 6:0 of this register
6:0	MR_THS_EXIT	R/W	0xB	Ths-exit value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.

6.2.1.48 CSI1_TPLX Register (Address = 0x68) [Reset = 0x06]

CSI1_TPLX is shown in Table 7-238.

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Table 7-238 CSI1_TPLX Register Field Descriptions

Bit	Field	Type	Reset	Description
7	MR_TPLX_OV	R/W	0x0	Override CSI-2 Tplx parameter 0: Tplx is automatically determined 1: Override Tplx with value in bits 6:0 of this register
6:0	MR_TPLX	R/W	0x6	Tplx value If bit 7 of this register is 0, this field is read-only, indicating current automatically determined value. The default value is based on the 800 Mbps CSI-2 rate and may change if different rate is selected. If bit 7 of this register is 1, this field is read/write.