ZHCSK36 August   2019 DS160PR410

ADVANCE INFORMATION for pre-production products; subject to change without notice.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 DC Electrical Characteristics
    6. 6.6 High Speed Electrical Characteristics
    7. 6.7 SMBUS/I2C Timing Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Linear Equalization
      2. 7.3.2 DC Gain
      3. 7.3.3 Receiver Detect State Machine
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active PCIe Mode
      2. 7.4.2 Active Buffer Mode
      3. 7.4.3 Standby Mode
    5. 7.5 Programming
      1. 7.5.1 Control and Configuration Interface
        1. 7.5.1.1 Pin Mode
          1. 7.5.1.1.1 Four-Level Control Inputs
        2. 7.5.1.2 SMBUS/I2C Register Control Interface
        3. 7.5.1.3 SMBus/I2C Master Mode Configuration (EEPROM Self Load)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIE x4 Lane Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DisplayPort Application
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.1 Linear Equalization

The DS160PR410 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. Table 1 shows available equalization boost through EQ0_ADDR0 and EQ1_ADDR1 control pins, when in Pin Control mode (EN_SMB=L0).

Table 1. Equalization Control Settings

EQUALIZATION SETTING TYPICAL EQ BOOST
INDEX EQ1_ADDR1 EQ0_ADDR0 @ 4 GHz @ 8 GHz
0 L0 L0 –0.3 –0.8
1 L0 L1 0.4 1.3
2 L0 L2 3.3 5.7
3 L0 L3 3.8 7.1
4 L1 L0 4.9 8.4
5 L1 L1 5.2 9.1
6 L1 L2 5.4 9.8
7 L1 L3 6.5 10.7
8 L2 L0 6.7 11.3
9 L2 L1 7.7 12.6
10 L2 L2 8.7 13.6
11 L2 L3 9.1 14.4
12 L3 L0 9.4 15.0
13 L3 L1 10.3 15.9
14 L3 L2 10.6 16.5
15 L3 L3 11.8 17.8

The equalization of the device can also be set by writing to SMBus/I2C registers in slave or master mode. Refer to the DS160PR410 Programming Guide (SNLU255) for details.