ZHCSLO3D July   2004  – October 2021 DAC5662

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 描述
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Resistance Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics, AC
    8. 6.8  Electrical Characteristics, DC
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Inputs and Timing
      1. 7.1.1 Digital Inputs
      2. 7.1.2 Input Interfaces
      3. 7.1.3 Dual-Bus Data Interface and Timing
      4. 7.1.4 Single-Bus Interleaved Data Interface and Timing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Transfer Function
        1. 8.3.1.1 Analog Outputs
      2. 8.3.2 Output Configurations
      3. 8.3.3 Differential With Transformer
      4. 8.3.4 Single-Ended Configuration
      5. 8.3.5 Reference Operation
        1. 8.3.5.1 Internal Reference
        2. 8.3.5.2 External Reference
      6. 8.3.6 Gain Setting Option
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Informmation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PFB|48
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.6 Gain Setting Option

The full-scale output current on the DAC5662 can be set two ways: either for each of the two DAC channels independently or for both channels simultaneously. For the independent gain set mode, the GSET pin (pin 42) must be low (i.e. connected to AGND). In this mode, two external resistors are required — one RSET connected to the BIASJ_A pin (pin 44) and the other to the BIASJ_B pin (pin 41). In this configuration, the user has the flexibility to set and adjust the full-scale output current for each DAC independently, allowing for the compensation of possible gain mismatches elsewhere within the transmit signal path.

Alternatively, bringing the GSET pin high (i.e. connected to AVDD), the DAC5662 switches into the simultaneous gain set mode. Now the full-scale output current of both DAC channels is determined by only one external RSET resistor connected to the BIASJ_A pin. The resistor at the BIASJ_B pin may be removed, however this is not required since this pin is not functional in this mode and the resistor has no effect on the gain equation.