ZHCSLO3D July   2004  – October 2021 DAC5662

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 描述
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Resistance Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics
    7. 6.7  Electrical Characteristics, AC
    8. 6.8  Electrical Characteristics, DC
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Inputs and Timing
      1. 7.1.1 Digital Inputs
      2. 7.1.2 Input Interfaces
      3. 7.1.3 Dual-Bus Data Interface and Timing
      4. 7.1.4 Single-Bus Interleaved Data Interface and Timing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Transfer Function
        1. 8.3.1.1 Analog Outputs
      2. 8.3.2 Output Configurations
      3. 8.3.3 Differential With Transformer
      4. 8.3.4 Single-Ended Configuration
      5. 8.3.5 Reference Operation
        1. 8.3.5.1 Internal Reference
        2. 8.3.5.2 External Reference
      6. 8.3.6 Gain Setting Option
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Informmation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • PFB|48
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC Specifications
Resolution 12 Bits
DC Accuracy(1)
INL Integral nonlinearity 1 LSB = IOUTFS/212, TA = 25°C -2 ±0.3 2 LSB
DNL Differential nonlinearity -2 ±0.2 2 LSB
Analog Output
Offset error 0.03 %FSR
Gain error With external reference ±0.25 %FSR
With internal reference ±0.5 %FSR
Minimum full-scale output current(2) 2 mA
Maximum full-scale output current(2) 20 mA
Gain mismatch With internal reference -2 0.07 +2 %FSR
Output voltage compliance range(3) -1 1.25 V
RO Output resistance 300 kΩ
CO Output capacitance 5 pF
Reference Output
Reference voltage 1.14 1.2 1.26 V
Reference output current(4) 100 nA
Reference Input
VEXTIO Input voltage 0.1 1.25 V
RI Input resistance 1 MΩ
Small signal bandwidth 300 kHz
CI Input capacitance 100 pF
Temperature Coefficients
Offset drift 0 ppm of FSR/°C
Gain drift With external reference ±50 ppm of FSR/°C
With internal reference ±50 ppm of FSR/°C
Reference voltage drift ±20 ppm/°C
(1) Measured differentially through 50 Ω to AGND.
(2) Nominal full-scale current, IOUTFS, equals 32x the IBIAS current.
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting in reduced reliability of the DAC5662 device. The upper limit of the output compliance is determined by the load resistors and full-scale output current. Exceeding the upper limit adversely affects distortion performance and intergral nonlinearity.
(4) Use an external buffer amplifier with high impedance input to drive any external load.