ZHCSLO3D
July 2004 – October 2021
DAC5662
PRODUCTION DATA
1
特性
2
应用
3
描述
4
Revision History
5
Pin Configurations and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Resistance Characteristics
6.5
Electrical Characteristics
6.6
Electrical Characteristics
6.7
Electrical Characteristics, AC
6.8
Electrical Characteristics, DC
6.9
Switching Characteristics
6.10
Typical Characteristics
7
Parameter Measurement Information
7.1
Digital Inputs and Timing
7.1.1
Digital Inputs
7.1.2
Input Interfaces
7.1.3
Dual-Bus Data Interface and Timing
7.1.4
Single-Bus Interleaved Data Interface and Timing
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
DAC Transfer Function
8.3.1.1
Analog Outputs
8.3.2
Output Configurations
8.3.3
Differential With Transformer
8.3.4
Single-Ended Configuration
8.3.5
Reference Operation
8.3.5.1
Internal Reference
8.3.5.2
External Reference
8.3.6
Gain Setting Option
8.4
Device Functional Modes
8.4.1
Sleep Mode
9
Application and Implementation
9.1
Application Informmation
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
接收文档更新通知
12.3
支持资源
12.4
Trademarks
12.5
静电放电警告
12.6
术语表
封装选项
请参考 PDF 数据表获取器件具体的封装图。
机械数据 (封装 | 引脚)
PFB|48
散热焊盘机械数据 (封装 | 引脚)
PFB|48
QFND166
订购信息
zhcslo3d_oa
zhcslo3d_pm
1
特性
12 位双路发送 DAC
275MSPS 更新速率
单电源:3V 至 3.6V
高 SFDR:5MHz 时为 85dBc
高 IMD3:15.1MHz 和 16.1MHz 时为 78dBc
WCDMA ACLR:30.72MHz 时为 70dB
独立或单一电阻器增益控制
双路或交错式数据
1.2V 片上基准电压
低功耗:330mW
断电模式:15mW
封装:48 引脚 TQFP