ZHCSEA8A October   2015  – October 2015

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Demodulator
      2. 7.3.2 PWM Control
        1. 7.3.2.1 PWM_CTRL Input
        2. 7.3.2.2 PWM1, PWM2
        3. 7.3.2.3 Self-Switching
        4. 7.3.2.4 Duty Cycle Adjustment
      3. 7.3.3 Current Sense Amplifier
      4. 7.3.4 Voltage Regulator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Transfer
        1. 7.4.1.1 Dynamic Power Limiting™
      2. 7.4.2 Communication
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 Current Monitoring Requirements
        3. 8.2.2.3 Input Regulation
        4. 8.2.2.4 System Input Power Requirements
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Notes
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
PVIN1, PVIN2 –0.3 7 V
BOOT1 (2) –0.3 14 V
VBOOT1 – VSW1 –0.3 7 V
BOOT2 (2) –0.3 14 V
VBOOT2 – VSW2 –0.3 7 V
PWM1, PWM2, EN, CLK_OUT, MODE, PWM_CTRL –0.3 3.6 V
DMIN1 –5 7 V
DMIN2 –0.3 7 V
CSN, CSP –0.3 7 V
CSN to CSP -0.5 0.5 V
Operating junction temperature, TJ –40 125 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) In normal use, BOOT1, BOOT2 voltage internally regulated.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PVIN1, PVIN2 4.5 5 5.5 V
PWM1, PWM2, EN, CLK_OUT, MODE, PWM_CTRL 0 3 3.3 V
DMIN1 –0.3 5 V
DMIN2 –0.3 5 V
CBP3 BP3 ceramic capacitor 2.2 µF
CPVIN1, CPVIN2 PVIN1, PVIN2 ceramic capacitor 0.1 µF
CPVIN1, CPVIN2 PVIN1, PVIN2 electrolytic capacitor 22 µF
CBOOT1, CBOOT2 SW1-BOOT1, SW2-BOOT2 capacitor 0.1 µF

6.4 Thermal Information

THERMAL METRIC (1) bq50002 UNIT
QFN
32 PINS
RθJA Junction-to-ambient thermal resistance 40.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.1 °C/W
RθJB Junction-to-board thermal resistance 13.1 °C/W
ψJT Junction-to-top characterization parameter 0.8 °C/W
ψJB Junction-to-board characterization parameter 13.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

–40°C ≤ TJ ≤ 125°C, VPVIN1 = 5V, VPVIN2 = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
UVLO rising threshold VIN rising 3.75 3.90 4.20 V
UVLO falling threshold VIN falling 3.60 3.85 4.08 V
REGULATOR VOLTAGE (BP3)
BP3 output voltage IBP3 = –5 mA, VPVIN1 = VPVIN2 = 5.0 V 2.9 3.0 3.1 V
BP3 output voltage IBP3 = –10 mA, VPVIN1 = VPVIN2 = 5.0 V 2.9 3.0 3.1 V
BP3 load current max VBP3 = 2.7 V, VPVIN1 = VPVIN2 = 5.0 V 7.7 14 21 mA
CURRENT SENSE AMPLIFIER (CSP, CSN)
Current sense amplifier gain 0°C < TJ < 85°C 49 50 51 V/V
Current sense amplifier offset 0°C < TJ < 85°C -14 14 mV
Input current (CSP) VCSP = 5.0 V, VPVIN1 = VPVIN2 = 5.0 V 1.5 mA
Input current (CSN) VCSN = 5.0 V, VPVIN1 = VPVIN2 = 5.0 V 8.5 10.0 11.3 μA
EN
High-level input voltage Input rising 1.7 1.8 1.9 V
Low-level input voltage Input falling 0.8 1.0 1.1 V
EN pull-down resistance EN = 3 V 40 50 60 kΩ
PWM_CTRL
High-level input voltage Input rising 1.4 1.6 1.8 V
Low-level input voltage Input falling 0.9 1.0 1.1 V
PWM_CTRL pull-down resistance PWM_CTRL = 3 V 40 50 60 kΩ
PWM1
High-level input voltage Input rising 1.6 1.8 1.9 V
Low-level input voltage Input falling 0.9 1.0 1.1 V
PWM1 pull-down resistance PWM1 = 3 V 40 50 60 kΩ
PWM2
High-level input voltage Input rising 1.6 1.7 1.8 V
Low-level input voltage Input falling 1.0 1.1 1.2 V
PWM2 pull-down resistance PWM2 = 3 V 40 50 60 kΩ
MODE
High-level input voltage Input rising 1.7 1.8 1.9 V
Low-level input voltage Input falling 0.9 1.0 1.1 V
MODE pull-down resistance MODE = 3 V 40 50 60 kΩ
BOOTSTRAP DIODE (BOOT1 AND BOOT2)
Regulation voltage (BOOT1) VPVIN1 = VPVIN2 = 5 V, IBOOT = 0 mA 4.2 4.4 4.7 V
Regulation voltage (BOOT2) VPVIN1 = VPVIN2 = 5 V, IBOOT = 0 mA 4.9 5.0 5.1 V
UVLO (BOOT1) VPVIN1 = VPVIN2 = 5 V 1.8 2.3 2.7 V
UVLO (BOOT2) VPVIN1 = VPVIN2 = 5 V 1.8 2.2 2.6 V
MOSFETS (SW1 AND SW2)
SW1 high-side RDS(on) VPVIN1 = VPVIN2 = 5 V 59 76 107 mΩ
SW1 low-side RDS(on) VPVIN1 = VPVIN2 = 5 V 48 61 86 mΩ
SW2 high-side RDS(on) VPVIN1 = VPVIN2 = 5 V 42 49 64 mΩ
SW2 low-side RDS(on) VPVIN1 = VPVIN2 = 5 V, ISW = 500 mA 39 46 58 mΩ

6.6 Typical Characteristics

bq50002 SW1-2_sluscd3.png
Figure 1. bq50002 SW1, SW2
bq50002 DMOUT_sluscd3.png
Figure 2. DMOUT1, DMOUT2