ZHCSEA8A October   2015  – October 2015

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Demodulator
      2. 7.3.2 PWM Control
        1. 7.3.2.1 PWM_CTRL Input
        2. 7.3.2.2 PWM1, PWM2
        3. 7.3.2.3 Self-Switching
        4. 7.3.2.4 Duty Cycle Adjustment
      3. 7.3.3 Current Sense Amplifier
      4. 7.3.4 Voltage Regulator
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Transfer
        1. 7.4.1.1 Dynamic Power Limiting™
      2. 7.4.2 Communication
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 Current Monitoring Requirements
        3. 8.2.2.3 Input Regulation
        4. 8.2.2.4 System Input Power Requirements
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout Notes
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Layout

10.1 Layout Guidelines

Careful PCB layout practice is critical to proper system operation. Many references are available on proper PCB layout techniques. A few good tips are as follows.

The TX layout requires a 4-layer PCB layout for best ground plane technique. A 2-layer PCB layout can be achieved though not as easily. Ideally, the approach to the layer stack-up is:

  • Layer 1 component placement and as much ground plane as possible
  • Layer 2 clean ground
  • Layer 3 finish routing
  • Layer 4 clean ground

Thus, the circuitry is virtually sandwiched between grounds. This minimizes EMI noise emissions and also provides a noise-free voltage reference plane for device operation.

Keep as much copper as possible. Make sure the bq500511 GND pins have a continuous flood connection to the ground plane. The power pad of the bq50002 should also be stitched to the ground plane, which also acts as a heat sink. A good GND reference is necessary for proper system operation, such as analog-digital conversion, clock stability, and best overall EMI performance. Separate the analog ground plane from the power ground plane and use only one tie point to connect grounds. Having several tie points defeats the purpose of separating the grounds. See the bq500511 EVM for an example of a good layout technique.

10.1.1 Layout Notes

Make sure the bypass capacitors intended for the bq500511 3.3-V supply are actually bypassing these supply pins (pin 32, DVCC, and pin 40, AVCC) to solid ground plane (see Figure 11). This means they need to be placed as close to the device as possible and the traces must be as wide as possible.

Make sure the bq500511 has a continuous flood connection to the ground plane (see Figure 12).

The full-bridge power stage that drives the TX coil is composed of two half-bridge power stages (integrated in bq50002) and resonant capacitors. Inputs bypass capacitors should be placed as close as possible to the bq50002 PVIN1 pins (pin 27, 28) and PVIN2 pins (pin 14, 15). The input and ground pours and traces should be made as wide as possible for better current flow. The trace to the coil and resonant capacitors should also be made as wide as possible (see Figure 13).

To ensure proper operation, grounds conducting a large amount of current and switching noise must be isolated from low current, quiet grounds. Separate the ground pours for the power stages and the bq500511 IC. Connect all grounds to a single point at the main ground terminal (see Figure 14).

Proper current sensing layout technique is very important, as it directly affects the FOD and PMOD performance. When sampling the very-low voltages generated across a current sense resistor, be sure to use the so called 4- wire or Kelvin-connection technique. This is important to avoid introducing false voltage drops from adjacent pads and copper power routes. It is a common power-supply layout technique. Some high-accuracy sense resistors have dedicated sense pins (see Figure 15).

The trace from bq50002 CSP pin to sense resistor must be minimized to avoid unwanted offset in the application. This trace should be limited to less than 20 mΩ resistance.

10.2 Layout Examples

bq50002 layout1_lusbw1.gif Figure 11. Bypass Capacitors Layout
bq50002 Layout2_sluscd3.png Figure 12. Continuous GND Layout
bq50002 Layout3_sluscd3.png Figure 13. Ground Layout
bq50002 Layout4_sluscd3.png Figure 14. Ground Layout
bq50002 Layout5_sluscd3.png Figure 15. Current Sensing Layout