ZHCS624E december   2011  – april 2021 BQ2946

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Options
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Sense Positive Input for V1
      2. 8.3.2 Output Drive, OUT
      3. 8.3.3 Supply Input, VDD
      4. 8.3.4 Thermal Pad, PWRPAD
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 OVERVOLTAGE Mode
      3. 8.4.3 Customer Test Mode
  10.   Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Application Configuration
      2. 9.1.2 30
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Example
  11.   Power Supply Recommendations
  12. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 第三方产品免责声明
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  14.   Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.4.3 Customer Test Mode

Customer Test Mode (CTM) helps reduce test time for checking the overvoltage delay timer parameter once the circuit is implemented in the battery pack. To enter CTM, VDD should be set to at least 10 V higher than V1 (see Figure 8-2). The delay timer is greater than 10 ms, but considerably shorter than the timer delay in normal operation. To exit CTM, remove the VDD to V1 voltage differential of 10 V so that the decrease in this value automatically causes an exit.

CAUTION:

Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into CTM. Also avoid exceeding Absolute Maximum Voltage for the cell voltage (V1–VSS). Stressing the pins beyond the rated limits may cause permanent damage to the device.

Figure 8-2 shows the timing for the CTM.

GUID-81A3AC8E-6F21-4F46-B386-840C507CD407-low.gifFigure 8-2 Timing for Customer Test Mode

Figure 8-3 shows the measurement for current consumption for the product for both VDD and Vx.

GUID-7B6A24ED-5FF6-4A5D-AA74-6444104BA2BF-low.gifFigure 8-3 Configuration for IC Current Consumption Test