ZHCSCA6B April   2014  – October 2020 ADS4245-EP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics:
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics: LVDS And CMOS Modes
    9. 6.9  Typical Characteristics:
    10. 6.10 Typical Characteristics: General
    11. 6.11 Typical Characteristics: Contour
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Functions
      2. 7.4.2 Gain For SFDR/SNR Trade-Off
      3. 7.4.3 Offset Correction
      4. 7.4.4 Power-Down
        1. 7.4.4.1 Global Power-Down
        2. 7.4.4.2 Channel Standby
        3. 7.4.4.3 Input Clock Stop
      5. 7.4.5 Digital Output Information
        1. 7.4.5.1 Output Interface
        2. 7.4.5.2 DDR LVDS Outputs
        3. 7.4.5.3 LVDS Buffer
        4. 7.4.5.4 Parallel CMOS Interface
        5. 7.4.5.5 CMOS Interface Power Dissipation
        6. 7.4.5.6 Multiplexed Mode Of Operation
        7. 7.4.5.7 Output Data Format
      6. 7.4.6 Device Configuration
        1. 7.4.6.1 Parallel Configuration Only
        2. 7.4.6.2 Serial Interface Configuration Only
        3. 7.4.6.3 Using Both Serial Interface And Parallel Controls
        4. 7.4.6.4 Parallel Configuration Details
        5. 7.4.6.5 Serial Interface Details
          1. 7.4.6.5.1 Register Initialization
          2. 7.4.6.5.2 Serial Register Readout
    5. 7.5 Serial Register Map
    6. 7.6 Description Of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Clock Input
    2. 8.2 Typical Applications
      1. 8.2.1 Analog Input
        1. 8.2.1.1 Design Requirements for Drive Circuits
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding
      2. 10.1.2 Supply Decoupling
      3. 10.1.3 Exposed Pad
      4. 10.1.4 Routing Analog Inputs
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Support
        1. 11.1.1.1 Definition Of Specifications
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

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6.5 Electrical Characteristics:

Typical values are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, 50% clock duty cycle, –1dBFS differential analog input, LVDS interface, and 0dB gain (unless otherwise noted). Minimum and maximum values are across the recommended operating condition (unless otherwise noted), AVDD = 1.8V, and DRVDD = 1.8V.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
Resolution14Bits
Signal-to-noise ratioSNRfIN = 20MHz73.4dBFS
fIN = 70MHz6872.9dBFS
fIN = 100MHz72.6dBFS
fIN = 170MHz71.4dBFS
fIN = 300MHz69.3dBFS
Signal-to-noise and
distortion ratio		SINADfIN = 20MHz73.2dBFS
fIN = 70MHz6872.6dBFS
fIN = 100MHz72.3dBFS
fIN = 170MHz71.2dBFS
fIN = 300MHz68.5dBFS
Spurious-free dynamic rangeSFDRfIN = 20MHz88dBc
fIN = 70MHz7186dBc
fIN = 100MHz85dBc
fIN = 170MHz88dBc
fIN = 300MHz78dBc
Total harmonic distortionTHDfIN = 20MHz86dBc
fIN = 70MHz6884dBc
fIN = 100MHz83dBc
fIN = 170MHz84dBc
fIN = 300MHz75dBc
Second-harmonic distortionHD2fIN = 20MHz88dBc
fIN = 70MHz66.586dBc
fIN = 100MHz85dBc
fIN = 170MHz88dBc
fIN = 300MHz78dBc
Third-harmonic distortionHD3fIN = 20MHz93dBc
fIN = 70MHz72.589dBc
fIN = 100MHz89dBc
fIN = 170MHz90dBc
fIN = 300MHz81dBc
Worst spur
(other than second and third harmonics)		fIN = 20MHz95dBc
fIN = 70MHz7394dBc
fIN = 100MHz93dBc
fIN = 170MHz91dBc
fIN = 300MHz89dBc
Two-tone intermodulation distortionIMDf1 = 46MHz, f2 = 50MHz,
each tone at –7dBFS		96dBFS
f1 = 185MHz, f2 = 190MHz,
each tone at –7dBFS		92dBFS
Crosstalk20-MHz full-scale signal on channel under observation; 170-MHz full-scale signal on other channel95dB
Input overload recoveryRecovery to within 1%
(of full-scale) for 6dB overload with sine-wave input		1Clock cycle
AC power-supply rejection ratioPSRRFor 100mVPP signal on AVDD supply, up to 10MHz> 30dB
Effective number of bitsENOBfIN = 70MHz11.5LSBs
Differential nonlinearityDNLfIN = 70MHz–0.97±0.51.9LSBs
Integrated nonlinearityINLfIN = 70MHz±2±5LSBs