ZHCSCA6B April   2014  – October 2020 ADS4245-EP

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics:
    6. 6.6  Electrical Characteristics: General
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Characteristics: LVDS And CMOS Modes
    9. 6.9  Typical Characteristics:
    10. 6.10 Typical Characteristics: General
    11. 6.11 Typical Characteristics: Contour
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Functions
      2. 7.4.2 Gain For SFDR/SNR Trade-Off
      3. 7.4.3 Offset Correction
      4. 7.4.4 Power-Down
        1. 7.4.4.1 Global Power-Down
        2. 7.4.4.2 Channel Standby
        3. 7.4.4.3 Input Clock Stop
      5. 7.4.5 Digital Output Information
        1. 7.4.5.1 Output Interface
        2. 7.4.5.2 DDR LVDS Outputs
        3. 7.4.5.3 LVDS Buffer
        4. 7.4.5.4 Parallel CMOS Interface
        5. 7.4.5.5 CMOS Interface Power Dissipation
        6. 7.4.5.6 Multiplexed Mode Of Operation
        7. 7.4.5.7 Output Data Format
      6. 7.4.6 Device Configuration
        1. 7.4.6.1 Parallel Configuration Only
        2. 7.4.6.2 Serial Interface Configuration Only
        3. 7.4.6.3 Using Both Serial Interface And Parallel Controls
        4. 7.4.6.4 Parallel Configuration Details
        5. 7.4.6.5 Serial Interface Details
          1. 7.4.6.5.1 Register Initialization
          2. 7.4.6.5.2 Serial Register Readout
    5. 7.5 Serial Register Map
    6. 7.6 Description Of Serial Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Clock Input
    2. 8.2 Typical Applications
      1. 8.2.1 Analog Input
        1. 8.2.1.1 Design Requirements for Drive Circuits
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Grounding
      2. 10.1.2 Supply Decoupling
      3. 10.1.3 Exposed Pad
      4. 10.1.4 Routing Analog Inputs
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Support
        1. 11.1.1.1 Definition Of Specifications
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

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6.11 Typical Characteristics: Contour

All graphs are at +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock. 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

GUID-AB89E34C-0E60-42B4-8E3C-D78A7BB80650-low.gifFigure 6-33 Spurious-Free Dynamic Range (0dB Gain)
GUID-9E6B1926-5828-4EE8-B37E-C18A239689DF-low.gifFigure 6-35 Signal-To-Noise Ratio (0dB Gain)
GUID-F798AED9-C21E-41FB-843C-C3B07867FCF1-low.gifFigure 6-37 Signal-To-Noise Ratio (0dB Gain)
GUID-1D45F8FF-3DAF-4231-919F-DF026F34BEDD-low.gifFigure 6-34 Spurious-Free Dynamic Range (6dB Gain)
GUID-5580A7B7-6AFB-468B-8E8D-1FC4D8315106-low.gifFigure 6-36 Signal-To-Noise Ratio (6dB Gain)
GUID-49F4F192-AC50-4145-868F-AD8635C17AA6-low.gifFigure 6-38 Signal-To-Noise Ratio (6dB Gain)