At TA = +25°C, AVDD = 1.8V, DRVDD = 1.8V, maximum rated sampling frequency, sine wave input clock, 1.5VPP differential clock amplitude, 50% clock duty cycle, –1dBFS differential analog input, High-Performance Mode disabled, 0dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.
Input Frequency = 40MHz |
50mVPP Signal
Superimposed |
on Input Common−Mode Voltage
0.95V |
Figure 6-28 CMRR
vs Test Signal Frequency
AVDD = 1.8V |
Input
Frequency = 2.5MHz |
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Figure 6-30 Analog Power vs Sampling FrequencyFigure 6-32 Digital Power In Various Modes (LVDS)
Input Frequency = 10MHz |
50mVPP Signal Superimposed on
AVDD Supply |
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Figure 6-29 PSRR
vs Test Signal FrequencyFigure 6-31 Digital Power LVDS CMOS