The ADS1285 is a high-resolution, low-power analog-to-digital converter (ADC) designed for applications in energy exploration, geology, and seismic monitoring where low-power consumption and high resolution are required. The converter provides 32 bits of resolution spanning data rates from 125 SPS to 4000 SPS. The programmable gain amplifier (PGA) expands the system dynamic range by accepting signals ranging from ±2.5 V_PP to ±0.039 V_PP.

As illustrated in the Section 8.2, the ADC consists of the following sections: input multiplexer (MUX), programmable gain amplifier (PGA), unity-gain buffer, delta-sigma (ΔΣ) modulator, sample rate converter, infinite impulse response (IIR) high-pass filter (HPF), finite impulse response (FIR) low-pass filter (LPF), and an SPI-compatible serial interface used for both device configuration and conversion data readback.

The input multiplexer selects between inputs 1 and 2, and internal options designed for self-test, including an input-short option used to test offset and noise.

The input multiplexer is followed by a low-noise PGA. The PGA gain range is 1 to 16, with gains 32 and 64 provided as digital gains. The PGA is chopper-stabilized to reduce 1/f noise and input offset voltage. The PGA output connects to a buffer which drives the modulator. An external 10-nF capacitor, connected to PGA output pins CAPP and CAPN, provides an antialias filter for the input signal.

The PGA can be disabled to lower device power consumption by operating the ADC with the unity-gain buffer. External 47-nF capacitors connected to each buffer output filters the modulator sampling pulses.

The ΔΣ modulator measures the differential input signal (V_IN) against the differential reference voltage (V_REF). The modulator provides three reference voltage options (2.5 V, 4.096 V, or 5 V). The reference voltage is programmed by the user.

Modulator data are processed by the digital filter providing the final conversion result. The digital filter consists of a sinc filter followed by a programmable phase, FIR low-pass filter, and an IIR high-pass filter. The high-pass filter removes dc and low-frequency components from the data.

The sample rate converter (SRC) compensates clock frequency error by resampling the output data. The clock frequency compensation range is ±244 ppm with 7-ppb resolution.

User-programmable gain and offset calibration registers correct offset and gain errors.

The SYNC pin synchronizes the ADC. Synchronization has two modes of operation: pulse synchronization and continuous synchronization. The RESET pin resets the ADC, including user configuration settings. The pins are noise-resistant, Schmitt-trigger inputs to increase reliability in high-noise environments.

The PWDN pin powers down the ADC when not in use. The software power-down mode (STANDBY) is available through the serial interface

The 4-wire, SPI-compatible, serial interface reads conversion data and reads or writes device register data.

Two general-purpose digital I/Os are available for system level control.

Power for the PGA and buffer is supplied by AVDD1 and AVSS. A charge pump voltage regulator increases the input voltage range of the buffer that follows the PGA. Power for the modulator is supplied by AVDD2. IOVDD supplies the digital logic core through a 1.8-V low-dropout regulator (LDO). IOVDD is the digital I/O supply.