ZHCSQZ8A May   2022  – December 2022 ADS1285

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: 1.65 V ≤ IOVDD ≤ 1.95 V and 2.7 V ≤ IOVDD ≤ 3.6 V
    7. 6.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7 V ≤ IOVDD ≤ 3.6 V
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 PGA and Buffer
        1. 8.3.2.1 Programmable Gain Amplifier (PGA)
        2. 8.3.2.2 Buffer Operation (PGA Bypass)
      3. 8.3.3 Voltage Reference Input
      4. 8.3.4 IOVDD Power Supply
      5. 8.3.5 Modulator
        1. 8.3.5.1 Modulator Overdrive
      6. 8.3.6 Digital Filter
        1. 8.3.6.1 Sinc Filter Section
        2. 8.3.6.2 FIR Filter Section
        3. 8.3.6.3 Group Delay and Step Response
          1. 8.3.6.3.1 Linear Phase Response
          2. 8.3.6.3.2 Minimum Phase Response
        4. 8.3.6.4 HPF Stage
      7. 8.3.7 Clock Input
      8. 8.3.8 GPIO
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
      2. 8.4.2 Power-Down Mode
      3. 8.4.3 Reset
      4. 8.4.4 Synchronization
        1. 8.4.4.1 Pulse-Sync Mode
        2. 8.4.4.2 Continuous-Sync Mode
      5. 8.4.5 Sample Rate Converter
      6. 8.4.6 Offset and Gain Calibration
        1. 8.4.6.1 OFFSET Register
        2. 8.4.6.2 GAIN Register
        3. 8.4.6.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Output (DOUT)
        5. 8.5.1.5 Data Ready (DRDY)
      2. 8.5.2 Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1  Single Byte Command
        2. 8.5.3.2  WAKEUP: Wake Command
        3. 8.5.3.3  STANDBY: Software Power-Down Command
        4. 8.5.3.4  SYNC: Synchronize Command
        5. 8.5.3.5  RESET: Reset Command
        6. 8.5.3.6  Read Data Direct
        7. 8.5.3.7  RDATA: Read Conversion Data Command
        8. 8.5.3.8  RREG: Read Register Command
        9. 8.5.3.9  WREG: Write Register Command
        10. 8.5.3.10 OFSCAL: Offset Calibration Command
        11. 8.5.3.11 GANCAL: Gain Calibration Command
    6. 8.6 Register Map
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
        2. 8.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
        3. 8.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
        4. 8.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
        5. 8.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
        6. 8.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
        7. 8.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
        8. 8.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Analog Power Supplies
      2. 9.3.2 Digital Power Supply
      3. 9.3.3 Grounds
      4. 9.3.4 Thermal Pad
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RHB|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.3.2.1 Programmable Gain Amplifier (PGA)

The PGA is a low-noise, chopper-stabilized differential amplifier that extends the ADC dynamic range performance. The PGA provides analog gains from 1 to 16, with gains of 32 and 64 provided by digital scaling. The PGA output signal is routed to the CAPP and CAPN pins through 270-Ω resistors. Connect an external 10-nF, C0G-dielectric capacitor across these pins. An antialias filter is formed by these components to attenuate the signal level at the modulator aliasing frequency (fMOD).

As shown in Figure 8-4, the buffer is used between the PGA and the modulator. Connect two 47-nF, C0G-dielectric capacitors from each buffer output to AVSS (CAPBP and CAPBN). A voltage charge pump increases the buffer input voltage headroom. Connect an external 4.7-nF capacitor between CAPC and AGND for charge pump operation.

The PGA gain is programmed by the GAIN[2:0] bits of the CONFIG1 register. Table 8-2 shows the PGA gain settings and buffer selection. The PGA gains and input signal range are irrespective of the voltage reference.

Table 8-2 PGA Gains
GAIN[2:0] REGISTER BITS PGA GAIN INPUT SIGNAL RANGE (VPP)
000 1 ±2.5
001 2 ±1.25
010 4 ±0.625
011 8 ±0.3125
100 16 ±0.15625
101 32 ±0.078125
110 64 ±0.0390625
111 Buffer mode, gain = 1 ±2.5

Observe the PGA input and output voltage headroom specification. Figure 8-5 shows the input and output voltage headroom when operating with AVDD1 = 5 V, an input common-mode voltage (VCM) = 2.5 V, a differential input voltage = ±2.5 VPP, and at gain = 1. The absolute minimum and maximum PGA input voltage (1.25 V and 3.75 V) is ±1/2 of the differential signal voltage plus the common-mode voltage. The PGA provides 0.15-V input voltage margin at the negative peak and 0.4-V input voltage margin at the positive peak. As shown in the figure, the PGA gain increases by × 1.5 when the ADC is operated with 4.096-V or 5-V voltage references. The PGA provides 0.475-V output voltage margin at the positive and negative peaks.

Figure 8-5 PGA Headroom (AVDD1 = 5 V, PGA Gain = 1)

When operating with AVDD1 = 3.3 V, the PGA cannot support ±2.5-VPP input signals. Use the buffer for ±2.5-VPP input signals. For ±1.25-VPP input signals (PGA gain = 2), the input headroom is increased by increasing the common-mode voltage by 0.1 V to AVSS + 1.75 V. Figure 8-6 illustrates the input and output operating headroom for AVDD1 = 3.3 V, VCM = 1.75 V, input signal = ±1.25 VPP, and gain = 2. The PGA uses normal gain scaling when VREF = 2.5 V.

Figure 8-6 PGA Headroom (AVDD1 = 3.3 V, Gain = 2)