ZHCSQZ8A May   2022  – December 2022 ADS1285

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: 1.65 V ≤ IOVDD ≤ 1.95 V and 2.7 V ≤ IOVDD ≤ 3.6 V
    7. 6.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7 V ≤ IOVDD ≤ 3.6 V
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 PGA and Buffer
        1. 8.3.2.1 Programmable Gain Amplifier (PGA)
        2. 8.3.2.2 Buffer Operation (PGA Bypass)
      3. 8.3.3 Voltage Reference Input
      4. 8.3.4 IOVDD Power Supply
      5. 8.3.5 Modulator
        1. 8.3.5.1 Modulator Overdrive
      6. 8.3.6 Digital Filter
        1. 8.3.6.1 Sinc Filter Section
        2. 8.3.6.2 FIR Filter Section
        3. 8.3.6.3 Group Delay and Step Response
          1. 8.3.6.3.1 Linear Phase Response
          2. 8.3.6.3.2 Minimum Phase Response
        4. 8.3.6.4 HPF Stage
      7. 8.3.7 Clock Input
      8. 8.3.8 GPIO
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
      2. 8.4.2 Power-Down Mode
      3. 8.4.3 Reset
      4. 8.4.4 Synchronization
        1. 8.4.4.1 Pulse-Sync Mode
        2. 8.4.4.2 Continuous-Sync Mode
      5. 8.4.5 Sample Rate Converter
      6. 8.4.6 Offset and Gain Calibration
        1. 8.4.6.1 OFFSET Register
        2. 8.4.6.2 GAIN Register
        3. 8.4.6.3 Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Output (DOUT)
        5. 8.5.1.5 Data Ready (DRDY)
      2. 8.5.2 Conversion Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1  Single Byte Command
        2. 8.5.3.2  WAKEUP: Wake Command
        3. 8.5.3.3  STANDBY: Software Power-Down Command
        4. 8.5.3.4  SYNC: Synchronize Command
        5. 8.5.3.5  RESET: Reset Command
        6. 8.5.3.6  Read Data Direct
        7. 8.5.3.7  RDATA: Read Conversion Data Command
        8. 8.5.3.8  RREG: Read Register Command
        9. 8.5.3.9  WREG: Write Register Command
        10. 8.5.3.10 OFSCAL: Offset Calibration Command
        11. 8.5.3.11 GANCAL: Gain Calibration Command
    6. 8.6 Register Map
      1. 8.6.1 Register Descriptions
        1. 8.6.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0000b]
        2. 8.6.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 12h]
        3. 8.6.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 00h]
        4. 8.6.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
        5. 8.6.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
        6. 8.6.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
        7. 8.6.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
        8. 8.6.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Analog Power Supplies
      2. 9.3.2 Digital Power Supply
      3. 9.3.3 Grounds
      4. 9.3.4 Thermal Pad
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RHB|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.9 Typical Characteristics

at TA = 25°C, AVDD1 = 5 V, AVSS = 0 V, AVDD2 = 2.5 V, IOVDD = 1.8 V, fCLK = 8.192 MHz (4.096 MHz low-power mode), VREFP = 4.096 V, VREFN = 0 V, PGA gain = 1, VCM = 2.5 V, fDATA = 500 SPS (unless otherwise noted)

Shorted input, PGA gain = 1
Figure 6-9 High-Power Mode FFT Spectrum
Shorted input, PGA gain = 1, VREF = 2.5 V, AVDD1 = 3.3 V
Figure 6-11 High-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 1
Figure 6-13 High-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, buffer operation
 
Figure 6-15 High-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 8
Figure 6-17 High-Power Mode FFT Spectrum
Shorted input, PGA gain = 1
Figure 6-19 Mid-Power Mode FFT Spectrum
Shorted input, PGA gain = 1, VREF = 2.5 V, AVDD1 = 3.3 V
Figure 6-21 Mid-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 1
 
Figure 6-23 Mid-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 8
Figure 6-25 Mid-Power Mode FFT Spectrum
Shorted input, PGA gain = 1
Figure 6-27 Low-Power Mode FFT Spectrum
Shorted input, PGA gain = 1, VREF = 2.5 V, AVDD1 = 3.3 V
Figure 6-29 Low-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 1
 
Figure 6-31 Low-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 8
Figure 6-33 Low-Power Mode FFT Spectrum
AIN1 = fIN = 31.25 Hz, –0.5-dBFS signal, AIN2 = shorted
Figure 6-35 Channel-to-Channel Crosstalk
Mid-power mode
Figure 6-37 Dynamic Range vs PGA Gain
30 units
Figure 6-39 Offset Error Distribution
30 units
Figure 6-41 Gain Error Distribution
30 units
Figure 6-43 Gain Drift Distribution
30 units
Figure 6-45 Gain Match Distribution
VREF = 2.5 V, AVDD1 = 3.3 V, fIN = 31.25 Hz, VIN = –0.5 dBFS
Figure 6-47 Mid-Power Mode THD vs PGA Gain
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS
Figure 6-49 High-Power Mode THD vs PGA Gain
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS
Figure 6-51 Low-Power Mode THD vs PGA Gain
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS
Figure 6-53 Low-Power Mode THD vs Input Frequency
 
Figure 6-55 PGA Input Current Noise Distribution
 
 
Figure 6-57 Reference Input Current vs Temperature
 
 
Figure 6-59 CMRR vs Common-Mode Input Frequency
30 units
Figure 6-61 AVDD1 Current Distribution
 
 
Figure 6-63 AVDD1 Current vs Temperature
 
Figure 6-65 AVDD2 Current vs Temperature
 
Figure 6-67 IOVDD Current vs Data Rate
Shorted input, PGA gain = 8
Figure 6-10 High-Power Mode FFT Spectrum
RS = 1 kΩ
Figure 6-12 High-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 1
Figure 6-14 High-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 2, VREF = 2.5 V, AVDD1 = 3.3 V, 2048 data points
Figure 6-16 High-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 8
Figure 6-18 High-Power Mode FFT Spectrum
Shorted input, PGA gain = 8
Figure 6-20 Mid-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 1
Figure 6-22 Mid-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 2, VREF = 2.5 V, AVDD1 = 3.3 V, 2048 data points
Figure 6-24 Mid-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 8
Figure 6-26 Mid-Power Mode FFT Spectrum
Shorted input, PGA gain = 8
Figure 6-28 Low-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 1
Figure 6-30 Low-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –0.5 dBFS, PGA gain = 2, VREF = 2.5 V, AVDD1 = 3.3 V, 2048 data points
Figure 6-32 Low-Power Mode FFT Spectrum
fIN = 31.25 Hz, VIN = –20 dBFS, PGA gain = 8
Figure 6-34 Low-Power Mode FFT Spectrum
High-power mode
Figure 6-36 Dynamic Range vs PGA Gain
Low-power mode
Figure 6-38 Dynamic Range vs PGA Gain
30 units
Figure 6-40 Offset Drift Distribution
30 units
Figure 6-42 Gain Error Distribution
30 units
Figure 6-44 Gain Drift Distribution
VREF = 2.5 V, AVDD1 = 3.3 V, fIN = 31.25 Hz, VIN = –0.5 dBFS
Figure 6-46 High-Power Mode THD vs PGA Gain
VREF = 2.5 V, AVDD1 = 3.3 V, fIN = 31.25 Hz, VIN = –0.5 dBFS
Figure 6-48 Low-Power Mode THD vs PGA Gain
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS
Figure 6-50 Mid-Power Mode THD vs PGA Gain
VREF = 4.096 V, AVDD1 = 5 V, fIN = 31.25 Hz, VIN = –0.5 dBFS
Figure 6-52 High- and Mid-Power Mode THD vs Input Frequency
High-speed mode
Figure 6-54 PGA Input Current vs Input Voltage
High- and mid-power modes
 
Figure 6-56 Buffer Input Current vs Input Voltage
30 units
Figure 6-58 Reference Input Current Distribution
30 units
Figure 6-60 AVDD1 Current Distribution
 
 
Figure 6-62 AVDD1 Current vs Temperature
30 units
Figure 6-64 AVDD2 Current Distribution
 
Figure 6-66 PSRR vs Power-Supply Frequency