ZHCSES1B March 2016 – October 2018 ADS1282-SP
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSVD | MUX2 | MUX1 | MUX0 | CHOP | PGA2 | PGA1 | PGA0 |
0 |
Reset value = 08h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | Reserved | Always write '0' | ||
6:4 | MUX[2:0] | MUX Select
000: AINP1 and AINN1 (default) 001: AINP2 and AINN2 010: Internal short via 400Ω 011:AINP1 and AINN1 connected to AINP2 and AINN2 100: External short to AINN2 |
||
3 | CHOP | PGA Chopping Enable
0: PGA chopping disabled 1: PGA chopping enabled (default) |
||
2:0 | PGA[2:0] | PGA Gain Select
000: G = 1 (default) 001: G = 2 010: G = 4 011: G = 8 100: G = 16 101: G = 32 110: G = 64 |