ZHCSES1B March 2016 – October 2018 ADS1282-SP
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYNC | MODE | DR2 | DR1 | DR0 | PHASE | FILTR1 | FILTR0 |
Reset value = 52h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SYNC | Synchronization mode
0: Pulse SYNC mode (default) 1: Continuous SYNC mode |
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6 | MODE | 1: High-resolution mode (default) | ||
5:3 | DR[2:0] | Data Rate Select(1)
000: 250SPS 001: 500SPS 010: 1000SPS (default) 011: 2000SPS 100: 4000SPS |
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2 | PHASE | FIR Phase Response
0: Linear phase (default) 1: Minimum phase |
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1:0 | FILTR[1:0] | Digital Filter Select
Digital filter configuration 00: On-chip filter bypassed, modulator output mode 01: Sinc filter block only 10: Sinc + LPF filter blocks (default) 11: Sinc + LPF + HPF filter blocks |