9.2.2 Design Procedure

The following procedure can be followed to design the ADC31JB68 device into most applications:

• Choose an appropriate ADC driver and analog input interface.
  • Optimize the signal chain gain leading up to the ADC to make use of the full ADC dynamic range.
  • Identify whether DC or AC coupling is required.
  • Determine the desired analog input interface, such as a bandpass filter or a transformer.
  • Use the provided input network models to design and verify the interface.
  • Refer to the interface recommendations in Analog Input Considerations.
• Determine the core sampling rate of the ADC.
  • Must satisfy the bandwidth requirements of the application .
  • Must also provide enough margin to prevent aliasing or to accommodate the transitions bands of an anti-aliasing filter.
  • Ensure the application initialization sequence properly handles ADC core calibration as described in ADC Core Calibration.
• Determine the system latency requirements.
  • Total allowable latency through the ADC and JESD204B link.
  • Is the system tolerant of latency variation over time or conditions or between power cycles?
• Determine the desired JESD204B link configuration as discussed in JESD204B Supported Features.
  • Based on the system latency requirements, determine whether deterministic latency is required across the JESD204B link.
  • Choose the number of frames per multi-frame, K.
  • Choose whether scrambling is desired.
• Choose an appropriate clock generator, CLKIN interface, and SYSREF interface.
  • Determine the system clock distribution scheme and the clock frequencies for the CLKIN and SYSREF inputs.
  • Determine the allowable amount of sampling clock phase noise in the system and then select a CLKIN edge rate that satisfies this requirement as discussed in Internal Noise Sources.
  • Choose an appropriate CLKIN interface as discussed in Driving the CLKIN+ and CLKIN– Input.
  • Based on the latency requirements, determine whether SYSREF must meet setup and hold requirements relative to CLKIN.
  • Choose the SYSREF signal type as discussed in SYSREF Signaling.
  • Choose an appropriate SYSREF interface as discussed in Driving the SYSREF Input.
  • Choose a CLKIN and SYSREF clock generator based on the above requirements. The signals must come from the same generator in many cases.
• Design the SYNCb interface as discussed in Driving the SYNCb Input.
• Choose appropriate configurations for the output serial data interface.
  • Design the serial lane interface according to Output Serial-Lane Interface.
  • Choose the required PCB materials, keeping in mind the desired rate of the serial lanes.
  • Characterize the signal lane channels that connect the ADC serial output transmitters to the receiving device either through simulation or bench characterization.
  • Optimize the VOD and DEM parameters to achieve the required signal integrity according to Voltage Swing and De-Emphasis Optimization.
• Design the SPI bus interface.
  • Verify the electrical and functional compatibility of the ADC SPI with the SPI controller.
  • Interface the ADC to the SPI bus according to SPI.
  • Ensure that the application initialization sequence properly configures the output SDO voltage before the first read command.
• Design the power supply architecture and de-coupling.
  • Choose appropriate power supply and supply filtering devices to provide stable, low-noise supplies as described in Power Supply Recommendations.
  • Design the capacitive de-coupling around the ADC, also described in Power Supply Recommendations, while paying close attention to placing the capacitors as close to the device as possible.
  • Time the power architecture to satisfy the power sequence requirements described in Power Supply Design.
• Ensure that the application initialization sequence satisfies the JESD204B link initialization requirements described in JESD204B Link Initialization.
• Refer to Figure 78 for an example hardware design.